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1. 发明授权

US08557651B2 Method of manufacturing a semiconductor device using an etchant 有权
标题翻译：使用蚀刻剂制造半导体器件的方法
公开(公告)号：US08557651B2
公开(公告)日：2013-10-15
申请号：US13040472
申请日：2011-03-04
申请人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
发明人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
IPC分类号： H01L21/8238
CPC分类号： H01L21/28
摘要： In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.
摘要翻译：在蚀刻具有相对于电介质层的蚀刻选择性的封盖层的蚀刻剂中，封盖层改变介电层的组成，从而控制包括电介质层的栅电极的阈值电压。蚀刻剂包括约0.01至3重量％的酸，约10至40重量％的氟化物盐和溶剂。因此，通过用于去除封盖层的蚀刻工艺来防止电介质层损坏，并且提高了栅电极的电特性。

2. 发明申请

US20110217833A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING AN ETCHANT 有权
标题翻译：使用蚀刻剂制造半导体器件的方法
公开(公告)号：US20110217833A1
公开(公告)日：2011-09-08
申请号：US13040472
申请日：2011-03-04
申请人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
发明人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
IPC分类号： H01L21/28
CPC分类号： H01L21/28
摘要： In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.
摘要翻译：在蚀刻具有相对于电介质层的蚀刻选择性的封盖层的蚀刻剂中，封盖层改变介电层的组成，从而控制包括电介质层的栅电极的阈值电压。蚀刻剂包括约0.01至3重量％的酸，约10至40重量％的氟化物盐和溶剂。因此，通过用于去除封盖层的蚀刻工艺来防止电介质层损坏，并且提高了栅电极的电特性。

3. 发明申请

US20110201203A1 METHODS OF FORMING A HOLE HAVING A VERTICAL PROFILE AND SEMICONDUCTOR DEVICES HAVING A VERTICAL HOLE 有权
标题翻译：形成具有垂直剖面的孔的方法和具有垂直孔的半导体器件
公开(公告)号：US20110201203A1
公开(公告)日：2011-08-18
申请号：US13025410
申请日：2011-02-11
申请人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Seong-Ho Moon , So-Ra Han
发明人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Seong-Ho Moon , So-Ra Han
IPC分类号： H01L21/311
CPC分类号： H01L21/31111 , H01L21/32134 , H01L21/76802 , H01L27/10852 , H01L27/10876 , H01L27/10894 , H01L27/11578 , H01L27/11582 , H01L28/91 , H01L29/4236 , H01L29/66621 , H01L29/66833 , H01L29/7926
摘要： In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.
摘要翻译：在形成孔的方法中，在基板上形成绝缘层，通过绝缘层形成露出基板的预备孔。然后在基板上形成包含有机聚合物的感光层图案以填充预备孔。然后将包含氟化氢（HF）或氟（F2）的蚀刻气体提供到感光层图案上以蚀刻绝缘层，使得预备孔的宽度增加。

4. 发明申请

US20110159660A1 Methods of Forming Integrated Circuit Capacitors Having Sidewall Supports and Capacitors Formed Thereby 有权
标题翻译：形成具有侧壁支撑和形成电容器的集成电路电容器的方法
公开(公告)号：US20110159660A1
公开(公告)日：2011-06-30
申请号：US12906184
申请日：2010-10-18
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L21/02 , H01G13/00
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

5. 发明授权

US08344385B2 Vertical-type semiconductor device 有权
标题翻译：垂直型半导体器件
公开(公告)号：US08344385B2
公开(公告)日：2013-01-01
申请号：US12872270
申请日：2010-08-31
申请人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
发明人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
IPC分类号： H01L29/06 , H01L29/792
CPC分类号： H01L27/11578 , H01L27/11556 , H01L27/11582
摘要： In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern.
摘要翻译：在垂直型非易失性存储器件中，在衬底上设置绝缘层图案，绝缘层图案具有直线形状。单晶半导体图案设置在基板上以与绝缘层图案的两个侧壁接触，单晶半导体图案具有相对于基板在垂直方向上延伸的柱状。隧道氧化物层设置在单晶半导体图案上。在隧道氧化物层和衬底上提供下电极层图案。在下电极层图案上设置多个绝缘层间图案，绝缘层间图案沿着单晶半导体图案彼此隔开预定距离。在绝缘层间图案之间的隧道氧化物层上依次形成电荷捕获层和阻挡介质层。在绝缘夹层图案之间的阻挡介质层上设置多个控制栅极图案。在隧道氧化物层和最上层的绝缘层间图案上设置上电极层图案。

6. 发明授权

US08211804B2 Methods of forming a hole having a vertical profile and semiconductor devices having a vertical hole 有权
标题翻译：形成具有垂直剖面的孔的方法和具有垂直孔的半导体器件
公开(公告)号：US08211804B2
公开(公告)日：2012-07-03
申请号：US13025410
申请日：2011-02-11
申请人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Seong-Ho Moon , So-Ra Han
发明人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Seong-Ho Moon , So-Ra Han
IPC分类号： H01L21/311
CPC分类号： H01L21/31111 , H01L21/32134 , H01L21/76802 , H01L27/10852 , H01L27/10876 , H01L27/10894 , H01L27/11578 , H01L27/11582 , H01L28/91 , H01L29/4236 , H01L29/66621 , H01L29/66833 , H01L29/7926
摘要： In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.
摘要翻译：在形成孔的方法中，在基板上形成绝缘层，通过绝缘层形成露出基板的预备孔。然后在基板上形成包含有机聚合物的感光层图案以填充预备孔。然后将包含氟化氢（HF）或氟（F2）的蚀刻气体提供到感光层图案上以蚀刻绝缘层，使得预备孔的宽度增加。

7. 发明授权

US08119476B2 Methods of forming integrated circuit capacitors having sidewall supports and capacitors formed thereby 有权
标题翻译：形成具有侧壁支撑件的集成电路电容器和由此形成的电容器的方法
公开(公告)号：US08119476B2
公开(公告)日：2012-02-21
申请号：US12906184
申请日：2010-10-18
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

8. 发明授权

US08766343B2 Integrated circuit capacitors having sidewall supports 有权
标题翻译：具有侧壁支撑件的集成电路电容器
公开(公告)号：US08766343B2
公开(公告)日：2014-07-01
申请号：US13356032
申请日：2012-01-23
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

9. 发明申请

US20120112317A1 INTEGRATED CIRCUIT CAPACITORS HAVING SIDEWALL SUPPORTS 有权
标题翻译：集成电路电容器具有支持端口
公开(公告)号：US20120112317A1
公开(公告)日：2012-05-10
申请号：US13356032
申请日：2012-01-23
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

10. 发明申请

US20110073866A1 VERTICAL-TYPE SEMICONDUCTOR DEVICE 有权
标题翻译：垂直型半导体器件
公开(公告)号：US20110073866A1
公开(公告)日：2011-03-31
申请号：US12872270
申请日：2010-08-31
申请人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
发明人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
IPC分类号： H01L27/115
CPC分类号： H01L27/11578 , H01L27/11556 , H01L27/11582
摘要： In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern.
摘要翻译：在垂直型非易失性存储器件中，在衬底上设置绝缘层图案，绝缘层图案具有直线形状。单晶半导体图案设置在基板上以与绝缘层图案的两个侧壁接触，单晶半导体图案具有相对于基板在垂直方向上延伸的柱状。隧道氧化物层设置在单晶半导体图案上。在隧道氧化物层和衬底上设置下电极层图案。在下电极层图案上设置多个绝缘层间图案，绝缘层间图案沿着单晶半导体图案彼此隔开预定距离。在绝缘层间图案之间的隧道氧化物层上依次形成电荷捕获层和阻挡介质层。在绝缘夹层图案之间的阻挡介质层上设置多个控制栅极图案。在隧道氧化物层和最上层的绝缘层间图案上设置上电极层图案。

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