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1. 发明授权

US06496044B1 High-speed output circuit with low voltage capability 有权
标题翻译：具有低电压能力的高速输出电路
公开(公告)号：US06496044B1
公开(公告)日：2002-12-17
申请号：US10016950
申请日：2001-12-13
申请人： Hy V. Nguyen , Gubo Huang , Andy T. Nguyen
发明人： Hy V. Nguyen , Gubo Huang , Andy T. Nguyen
IPC分类号： H03K300
CPC分类号： H03K19/01721 , H03K19/00315
摘要： Output circuits that provide compatibility with various input and output voltage levels without sacrificing performance. A pull-up on an output terminal is gated by an internal node, and the invention encompasses various circuits and means for placing a data input signal on this internal node. One embodiment includes a level shifter on the data input path, while also providing an alternative path through the output circuit that bypasses the level shifter. When the input data value goes high, the alternative path quickly places an attenuated high value on the internal node. The level shifter then becomes active and raises the voltage on the internal node to the output power high level, ensuring that the output pull-up is completely off.
摘要翻译：输出电路，提供与各种输入和输出电压电平的兼容性，而不会牺牲性能。输出端子上的上拉由内部节点门控，本发明包括用于在该内部节点上放置数据输入信号的各种电路和装置。一个实施例包括数据输入路径上的电平移位器，同时还提供绕过电平移位器的输出电路的替代路径。当输入数据值变高时，替代路径会快速地将衰减的高值放在内部节点上。电平移位器然后变为有效，并将内部节点上的电压提高到输出功率高电平，确保输出上拉完全关闭。

2. 发明授权

US06628151B1 Self-regulating high voltage ramp up circuit 有权
标题翻译：自调节高压斜升电路
公开(公告)号：US06628151B1
公开(公告)日：2003-09-30
申请号：US10136115
申请日：2002-04-30
申请人： Shi-dong Zhou , Gubo Huang , Andy T. Nguyen
发明人： Shi-dong Zhou , Gubo Huang , Andy T. Nguyen
IPC分类号： H03K406
CPC分类号： H03K17/223 , H03K4/50
摘要： A self-regulating ramp up circuit generates a high voltage signal having a slow, smooth ramp up and reduced process and temperature variation. The circuit uses a resistor and a capacitor to control the rate at which the output signal changes state. In one embodiment, an enable signal operating at a low voltage level is shifted to the desired high voltage level using a level shifter. The resulting value is inverted using an inverter operating at the high voltage level and having a resistor in the pulldown path. The circuit output node is coupled to the output node of the inverter through a capacitor, and to the high voltage power supply through a pullup gated by the output node of the inverter. In some embodiments, the ramp up circuit forms a portion of a programmable logic device (PLD), and the capacitor and/or resistor have programmable capacitance/resistance values.
摘要翻译：自调节斜坡电路产生具有缓慢，平滑的上升和降低的工艺和温度变化的高电压信号。电路使用电阻和电容来控制输出信号变化的速率。在一个实施例中，使用电平移位器将在低电压电平下工作的使能信号转换到期望的高电压电平。使用在高电压电平下工作并在下拉路径中具有电阻器的逆变器来反转所得到的值。电路输出节点通过电容器耦合到逆变器的输出节点，并通过由逆变器的输出节点选通的上拉电路连接到高压电源。在一些实施例中，斜坡上升电路形成可编程逻辑器件（PLD）的一部分，并且电容器和/或电阻器具有可编程的电容/电阻值。

3. 发明授权

US07479805B1 Programmable differential signaling system 有权
标题翻译：可编程差分信号系统
公开(公告)号：US07479805B1
公开(公告)日：2009-01-20
申请号：US11888790
申请日：2007-08-01
申请人： Shi-dong Zhou , Gubo Huang , Andy T. Nguyen , Ronald L. Cline
发明人： Shi-dong Zhou , Gubo Huang , Andy T. Nguyen , Ronald L. Cline
IPC分类号： H03K19/0175
CPC分类号： H04L25/028 , H04L25/0264 , H04L25/0272 , H04L25/0288
摘要： A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.
摘要翻译：可编程差分信号系统包括可编程偏置发生器和多个输入/输出模块。可编程偏置发生器被可操作地耦合以基于多个差分信号约定中的一个的期望信号特性产生第一全局偏置信号和第二全局信号。多个输入/输出模块可操作地耦合以在差分信令和单端信令之间进行转换，其中基于第一和第二全局偏置信号来调节差分信令的实际信号特性以基本上等于期望的信号特性。

4. 发明授权

US07279982B1 Apparatus and method for low current differential swing I/O interface 有权
标题翻译：低电流差动摆幅I / O接口的装置和方法
公开(公告)号：US07279982B1
公开(公告)日：2007-10-09
申请号：US11089848
申请日：2005-03-24
申请人： Shi-dong Zhou , Andy T. Nguyen , Gubo Huang
发明人： Shi-dong Zhou , Andy T. Nguyen , Gubo Huang
IPC分类号： H03F3/04
CPC分类号： H03F3/45475 , H03F2203/45138 , H04L25/0272 , H04L25/0282 , H04L25/0292
摘要： Low current differential signal/swing I/O interfaces and techniques can be implemented. An output interface converts input data signals to differential current signals for transmission over transmission lines. When the differential current signals are received by an input interface, they are converted to differential voltage signals and appropriately amplified.
摘要翻译：可实现低电流差分信号/摆幅I / O接口和技术。输出接口将输入数据信号转换为差分电流信号，以通过传输线传输。当差分电流信号由输入接口接收时，它们被转换成差分电压信号并被适当放大。

5. 发明授权

US07265586B1 Programmable differential signaling system 有权
标题翻译：可编程差分信号系统
公开(公告)号：US07265586B1
公开(公告)日：2007-09-04
申请号：US11067422
申请日：2005-02-25
申请人： Shi-dong Zhou , Gubo Huang , Andy T. Nguyen , Ronald L. Cline
发明人： Shi-dong Zhou , Gubo Huang , Andy T. Nguyen , Ronald L. Cline
IPC分类号： H03K19/0175
CPC分类号： H04L25/028 , H04L25/0264 , H04L25/0272 , H04L25/0288
摘要： A programmable differential signaling system includes a programmable bias generator and a plurality of input/output modules. The programmable bias generator is operably coupled to generate a first global bias signal and a second global signal based on desired signal properties of one of a plurality of differential signaling conventions. The a plurality of input/output modules is operably coupled to convert between differential signaling and single ended signaling, wherein actual signal properties of the differential signaling are regulated based on the first and second global bias signals to substantially equal the desired signal properties.
摘要翻译：可编程差分信号系统包括可编程偏置发生器和多个输入/输出模块。可编程偏置发生器被可操作地耦合以基于多个差分信号约定中的一个的期望信号特性产生第一全局偏置信号和第二全局信号。多个输入/输出模块可操作地耦合以在差分信令和单端信令之间进行转换，其中基于第一和第二全局偏置信号来调节差分信令的实际信号特性以基本上等于期望的信号特性。

6. 发明授权

US06980035B1 Auto-detect level shifter for multiple output voltage standards 有权
标题翻译：自动检测电平移位器用于多种输出电压标准
公开(公告)号：US06980035B1
公开(公告)日：2005-12-27
申请号：US10391927
申请日：2003-03-18
申请人： Shi-dong Zhou , Gubo Huang , Shankar Lakkapragada , Andy T. Nguyen , Fariba Farahanchi
发明人： Shi-dong Zhou , Gubo Huang , Shankar Lakkapragada , Andy T. Nguyen , Fariba Farahanchi
IPC分类号： H03B1/00 , H03K3/00 , H03K3/356 , H03K19/0185
CPC分类号： H03K19/018585 , H03K3/356113
摘要： A technique and circuit implementation are described for automatically detecting a change in a power supply voltage and selectively reconfiguring a circuit for optimized performance at the changed voltage. One application of particular interest is an auto-detect level shifter. The auto-detect level shifter can be used in an output driver and can be automatically enabled if it is needed to optimize performance for various I/O standards, including those that operate at different voltages.
摘要翻译：描述了一种技术和电路实现，用于自动检测电源电压的变化，并选择性地重新配置电路以在改变的电压下优化性能。特别感兴趣的一个应用是自动检测电平移位器。自动检测电平转换器可用于输出驱动器，如果需要优化各种I / O标准（包括在不同电压下工作的I / O标准）的性能，可以自动启用。

7. 发明授权

US06960937B1 Power-up and enable control circuits for interconnection arrays in programmable logic devices 有权
标题翻译：上电并启用可编程逻辑器件中互连阵列的控制电路
公开(公告)号：US06960937B1
公开(公告)日：2005-11-01
申请号：US10977566
申请日：2004-10-29
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03K19/00 , H03K19/177 , H03K19/02 , H03K19/094
CPC分类号： H03K19/17748 , H03K19/0016 , H03K19/17736
摘要： Area-efficient power-up and enable control circuits useful in PLD interconnection arrays. A control circuit can include a driver circuit, first and second pull-ups, and first and second pull-downs. The driver circuit has an output terminal coupled to a control circuit output terminal. The first and second pull-ups are coupled in series between the control circuit output terminal and power high. The first pull-up has a gate terminal coupled to an enable terminal. The second pull-up has a gate terminal coupled to a pull-up control terminal. The first and second pull-downs are coupled in parallel between the control circuit output terminal and ground. The first pull-down has a gate terminal coupled to the enable terminal. The second pull-down has a gate terminal coupled to a pull-down control terminal. In other embodiments, the first and second pull-ups are coupled in parallel, and the first and second pull-downs are coupled in series.
摘要翻译：区域高效的上电，并使控制电路在PLD互连阵列中有用。控制电路可以包括驱动器电路，第一和第二上拉以及第一和第二下拉。驱动器电路具有耦合到控制电路输出端子的输出端子。第一和第二上拉串联在控制电路输出端和电源高电平之间。第一上拉具有耦合到使能端的栅极端子。第二上拉具有耦合到上拉控制端子的栅极端子。第一和第二下拉在控制电路输出端和地之间并联耦合。第一下拉具有耦合到使能端的栅极端子。第二下拉具有耦合到下拉控制端子的栅极端子。在其他实施例中，第一和第二上拉并联耦合，第一和第二下拉串联耦合。

8. 发明授权

US06914460B1 Counter-based clock doubler circuits and methods 有权
标题翻译：基于计数器的时钟倍增电路和方法
公开(公告)号：US06914460B1
公开(公告)日：2005-07-05
申请号：US10719830
申请日：2003-11-20
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： G06F7/68 , H03B19/00 , H03H11/16 , H03K5/156
CPC分类号： G06F7/68 , H03K5/1565
摘要： Clock doubler circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the counted value is stored. The stored value is divided by two to provide the number of counts in half of the input clock period. The divided value is provided to a second counter that counts from zero to the divided value. Thus, the second counter generates a pulse halfway through the input clock period. Other counters running at the same clock rate can be used to generate pulses at other times in the input clock cycle, as desired. The pulses from the counters are used to provide output clock edges at predetermined times during the input clock cycle.
摘要翻译：时钟倍增器电路和方法使用计数器来定义输出时钟边沿的位置。多个计数器各自由比输入时钟快得多的计数时钟计时。第一个计数器计数一个输入时钟周期，并存储计数值。将存储的值除以2以将计数数量设置为输入时钟周期的一半。分割值被提供给从零计数到分割值的第二计数器。因此，第二计数器在输入时钟周期的中途产生脉冲。按照相同时钟速率运行的其他计数器可以根据需要用于在输入时钟周期的其他时间产生脉冲。来自计数器的脉冲用于在输入时钟周期内以预定时间提供输出时钟边沿。

9. 发明授权

US06707331B1 High speed one-shot circuit with optional correction for process shift 有权
标题翻译：高速单脉冲电路，可选择校正过程漂移
公开(公告)号：US06707331B1
公开(公告)日：2004-03-16
申请号：US10199145
申请日：2002-07-19
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03K501
CPC分类号： H03K5/04 , H03K5/133
摘要： A one-shot circuit provides a pulse on receipt of a first edge, and removes the pulse after a delay generated by a delay chain. However, a second, opposite edge resets the circuit without an intervening delay chain delay. The delay chain can be implemented using a chain of AND circuits (one-shot high) or OR circuits (one-shot low), each driven by the preceding circuit in the chain and by the input signal. In some embodiments, an output circuit includes a pass gate coupled between the one-shot input and output terminals and a pulldown (one-shot high) or pullup (one-shot low) that provides an inactive value when the pulse is not being applied. The pass gate and pullup or pulldown are controlled by the output of the daisy chain. Other embodiments offer programmable capabilities, such as the ability to correct for process shift by altering the effective delay of the delay chain.
摘要翻译：单触发电路在接收到第一边缘时提供脉冲，并且在由延迟链产生的延迟之后去除脉冲。然而，第二个相反的边缘复位电路，而没有中间延迟链延迟。延迟链可以使用一系列AND电路（单次高电平）或OR电路（一次性低电平）来实施，每个电路由链中的前一个电路和输入信号驱动。在一些实施例中，输出电路包括耦合在单触发输入和输出端子之间的通过栅极以及当不施加脉冲时提供无效值的下拉（单次高电平）或上拉（一次低电平）。传递门和上拉或下拉由菊花链的输出控制。其他实施例提供可编程能力，例如通过改变延迟链的有效延迟来校正过程偏移的能力。

10. 发明授权

US06566918B1 Divide-by-N clock divider circuit with minimal additional delay 有权
标题翻译：具有最小额外延迟的N / D分频电路
公开(公告)号：US06566918B1
公开(公告)日：2003-05-20
申请号：US10210938
申请日：2002-08-02
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03K2138
CPC分类号： G06F1/08 , G06F7/68 , H03K23/00
摘要： A divide-by-N clock divider circuit adds little additional delay on the clock path. N can be any integer, and the value of N does not affect the clock path delay. The divide-by-N clock divider circuits of the invention include a control circuit and a logical NOR circuit, where the control circuit is clocked by an input clock signal and the NOR circuit combines the output signal of the control circuit with the input clock signal. The control circuit acts as a filter, selecting pulses from the input clock signal to be passed to the output terminal. By selecting one out of every N input clock pulses, a divide-by-N clock divider is implemented. Because no decode logic is included in the clock path, the through-delay of the clock divider circuit is small. In some embodiments, the value of N is programmable. In some embodiments, optional duty cycle correction is available.
摘要翻译： N分频电路在时钟路径上增加了一些额外的延迟。 N可以是任何整数，N的值不影响时钟路径延迟。本发明的分频N分频电路包括控制电路和逻辑或非电路，其中控制电路由输入时钟信号计时，而NOR电路将控制电路的输出信号与输入时钟信号。控制电路作为滤波器，从输入时钟信号中选择要传递到输出端的脉冲。通过选择每N个输入时钟脉冲中的一个，实现了一个除以N个时钟分频器。由于时钟路径中不包含解码逻辑，因此时钟分频电路的通过延迟很小。在一些实施例中，N的值是可编程的。在一些实施例中，可选择的占空比校正是可用的。

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