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1. 发明授权

US07372679B1 Method and apparatus for RC triggered electrostatic discharge power clamp with hysteresis 有权
标题翻译：具有迟滞功能的RC触发静电放电电源钳的方法和装置
公开(公告)号：US07372679B1
公开(公告)日：2008-05-13
申请号：US10871070
申请日：2004-06-18
申请人： Fu-Hing Ho , Patrick J. Crotty , Andy T. Nguyen
发明人： Fu-Hing Ho , Patrick J. Crotty , Andy T. Nguyen
IPC分类号： H02H3/22
CPC分类号： H02H9/046 , H01L27/0285
摘要： An Electrostatic Discharge (ESD) protection device extends the protection range of an ESD clamp circuit through hysteresis of the associated ESD clamp control circuit. Once the ESD clamp circuit is activated, an adjustment circuit applies a trigger level adjustment signal to the ESD clamp control circuit. The trigger level adjustment signal effectively increases the magnitude of the deactivation signal that is required to deactivate the ESD clamp circuit. Since the deactivation signal increases over time, a longer activation time of the ESD protection device is provided, which allows an extended protection range.
摘要翻译：静电放电（ESD）保护装置通过相关ESD钳位控制电路的滞后来延长ESD钳位电路的保护范围。一旦ESD钳位电路被激活，调整电路就向ESD钳位控制电路施加触发电平调整信号。触发电平调整信号有效地增加去激活ESD钳位电路所需的去激活信号的幅度。由于去激活信号随着时间的推移而增加，所以提供了ESD保护装置的较长的激活时间，这允许扩展的保护范围。

2. 发明授权

US07317333B1 Large loading split I/O driver with negligible crowbar 有权
标题翻译：大容量分流I / O驱动器，可以忽略不计
公开(公告)号：US07317333B1
公开(公告)日：2008-01-08
申请号：US11055228
申请日：2005-02-10
申请人： Shi-dong Zhou , Andy T. Nguyen
发明人： Shi-dong Zhou , Andy T. Nguyen
IPC分类号： H03K19/0175
CPC分类号： H03K19/0013 , H03K19/018528
摘要： A pre-driver for large I/O pull-up and pull-down transistors is provided so that the I/O pull-up and pull-down transistors do not experience crowbar current, and the pre-driver circuit likewise does not experience crowbar current or require large driver transistors. One pre-driver circuit includes two NAND gates and two NOR gates with delay circuitry provided by two series inverters from a data input to a first node, and two additional series inverters from the first node to a second node. A further pre-driver circuit includes feedback from the pre-driver outputs to ensure its NMOS and PMOS transistors do not turn on together to create crowbar, while allowing faster switching. With the pre-driver circuit embodiments, a conventional level shifter can be used. Further with the pre-driver circuitry, slew rate control can be provided in the pull-up and pull-down driver circuitry, rather than in the pre-driver circuitry.
摘要翻译：提供了用于大型I / O上拉和下拉晶体管的预驱动器，使得I / O上拉和下拉晶体管不会遇到撬棒电流，并且预驱动器电路同样不会遇到撬棒电流或需要大的驱动晶体管。一个预驱动器电路包括两个NAND门和两个NOR门，其中具有从数据输入到第一节点的两个串联反相器提供的延迟电路，以及从第一节点到第二节点的两个附加的串联反相器。进一步的预驱动电路包括来自预驱动器输出的反馈，以确保其NMOS和PMOS晶体管不会一起导通，以创建撬棒，同时允许更快的切换。利用预驱动器电路实施例，可以使用传统的电平转换器。此外，通过预驱动器电路，可以在上拉和下拉驱动器电路中提供压摆率控制，而不是在预驱动器电路中。

3. 发明授权

US07233184B1 Method and apparatus for a configurable latch 有权
标题翻译：用于可配置锁存器的方法和装置
公开(公告)号：US07233184B1
公开(公告)日：2007-06-19
申请号：US11158523
申请日：2005-06-22
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03K3/12
CPC分类号： H03K3/356156 , H03K3/35625 , H03K17/002 , H03K19/173
摘要： A configurable latch comprises a dual master stages arranged in parallel to share a single output node. The configurable latch provides a single slave stage at the single output node to be shared between the two master stages. Pass gates controlled by various phases of an input clock, controls access to the slave stage by the two master stages. Additional control is added to configure the latch for positive edge triggered and negative edge triggered flip-flop functionality as well as level sensitive functionality. Chip enable, set, and reset are also provided for additional control.
摘要翻译：可配置锁存器包括并行布置以共享单个输出节点的双主级。可配置锁存器在单个输出节点处提供单个从属级，以在两个主级之间共享。由输入时钟的各个相位控制的通道控制由两个主级进入从动级。添加附加控制以配置上升沿触发和负沿触发触发器功能的锁存器以及电平敏感功能。还提供芯片使能，置位和复位以进行附加控制。

4. 发明授权

US07157953B1 Circuit for and method of employing a clock signal 有权
标题翻译：电路和采用时钟信号的方法
公开(公告)号：US07157953B1
公开(公告)日：2007-01-02
申请号：US11104347
申请日：2005-04-12
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03K3/00
CPC分类号： H03M9/00 , H03K5/00006
摘要： The circuits and methods of the present invention relate to circuits for generating a multiplied clock signal based upon a reference clock signal, and circuits using the clock signal to deserialize data. According to one embodiment of the invention, a circuit comprising a counter is coupled to generate a count representative of the period of the input clock signal. A divider circuit coupled to the counter generates a divided count. Finally, a clock generator coupled to the divider circuit outputs an output clock signal having a period which is based upon the divided count. According to other embodiments, circuits and methods disclose receiving serial data using the output clock signal, and outputting the data as parallel data using the reference clock.
摘要翻译：本发明的电路和方法涉及用于基于参考时钟信号产生相乘时钟信号的电路，以及使用时钟信号反序列化数据的电路。根据本发明的一个实施例，包括计数器的电路被耦合以产生表示输入时钟信号的周期的计数。耦合到计数器的分频器电路产生分割计数。最后，耦合到除法器电路的时钟发生器输出具有基于划分的计数的周期的输出时钟信号。根据其他实施例，电路和方法公开了使用输出时钟信号接收串行数据，并且使用参考时钟将数据作为并行数据输出。

5. 发明授权

US07071738B1 Glitchless clock selection circuit using phase detection switching 有权
标题翻译：无差频时钟选择电路采用相位检测切换
公开(公告)号：US07071738B1
公开(公告)日：2006-07-04
申请号：US10877620
申请日：2004-06-24
申请人： Andy T. Nguyen , Shi-dong Zhou
发明人： Andy T. Nguyen , Shi-dong Zhou
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： A clock selection circuit includes an output multiplexer, control logic, and edge detection logic. The multiplexer includes inputs to receive multiple input clock signals, an output to generate the output clock signal, and a control terminal to receive a synchronized clock select signal. The control logic includes a first input to receive a clock select signal, a second input to receive a first control clock signal, a third input to receive a synchronization signal, and an output to selectively update the synchronized clock select signal with transitions in the clock select signal. The edge detection logic includes first inputs to receive the multiple input clock signals, a second input to receive a second control clock signal, and an output to generate the synchronization signal.
摘要翻译：时钟选择电路包括输出多路复用器，控制逻辑和边缘检测逻辑。多路复用器包括用于接收多个输入时钟信号的输入端，用于产生输出时钟信号的输出端和用于接收同步时钟选择信号的控制端子。控制逻辑包括用于接收时钟选择信号的第一输入端，用于接收第一控制时钟信号的第二输入端，接收同步信号的第三输入端和用于选择性地更新具有时钟转换的同步时钟选择信号的输出端选择信号。边缘检测逻辑包括用于接收多个输入时钟信号的第一输入端，用于接收第二控制时钟信号的第二输入端和产生同步信号的输出端。

6. 发明授权

US06853698B1 Ripple counter circuits and methods providing improved self-testing functionality 有权
标题翻译：纹波计数器电路和方法提供改进的自检功能
公开(公告)号：US06853698B1
公开(公告)日：2005-02-08
申请号：US10829065
申请日：2004-04-20
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： G01R31/3185 , H03K21/40 , H03K23/58 , H03K17/00
CPC分类号： G01R31/318527 , H03K21/40 , H03K23/58
摘要： A ripple counter circuit supports two modes of operation, a user mode and a test mode. In the user mode, the circuit functions as a standard ripple counter, counting in response to first edges (e.g., rising edges) on a clock input signal. In the test mode, the ripple counter circuit alternates between two states. In the first state, the bits all toggle from their initialization values to new values. In the second state, the circuit operates in the same fashion as the user mode. Therefore, the ripple counter circuit counts by one, returning all of the bits to their initialization values. This capability significantly simplifies the testing process, particularly for long ripple counters. Some embodiments of the invention include various control circuits coupled to provide an internal clock signal and/or an initialization signal.
摘要翻译：波纹计数器电路支持两种操作模式，用户模式和测试模式。在用户模式下，电路作为标准纹波计数器起作用，响应时钟输入信号上的第一个边缘（例如上升沿）进行计数。在测试模式下，纹波计数器电路在两种状态之间交替显示。在第一个状态下，这些位都从初始化值切换到新值。在第二状态下，电路以与用户模式相同的方式工作。因此，纹波计数器电路计数1，将所有位返回到其初始化值。该功能大大简化了测试过程，特别是对于长纹波计数器。本发明的一些实施例包括耦合以提供内部时钟信号和/或初始化信号的各种控制电路。

7. 发明授权

US06847241B1 Delay lock loop using shift register with token bit to select adjacent clock signals 有权
标题翻译：延迟锁定环使用带有令牌位的移位寄存器来选择相邻的时钟信号
公开(公告)号：US06847241B1
公开(公告)日：2005-01-25
申请号：US10627457
申请日：2003-07-25
申请人： Andy T. Nguyen , Shi-dong Zhou
发明人： Andy T. Nguyen , Shi-dong Zhou
IPC分类号： H03L7/081 , H03L7/06
CPC分类号： H03L7/0814
摘要： Delay lock loop (DLL) circuits, systems, and methods providing glitch-free output clock signals. Glitches are eliminated from an output clock signal by using shift registers including a single token bit to select one of many delayed clock signals. A DLL clock multiplexer includes a series of shift registers, each of which selects only one of the many input clock signals at each stage. Thus, only one clock signal is selected at any given time. Delay is added or subtracted from the loop by shifting the token bit within each shift register. The token bit is shifted by a single position at a time. Therefore, no glitching occurs.
摘要翻译：提供无毛刺输出时钟信号的延迟锁定环（DLL）电路，系统和方法。通过使用包括单个令牌位的移位寄存器来选择许多延迟时钟信号之一，从输出时钟信号中消除毛刺。 DLL时钟多路复用器包括一系列移位寄存器，每个移位寄存器在每个阶段只选择许多输入时钟信号中的一个。因此，在任何给定时间仅选择一个时钟信号。通过移位每个移位寄存器中的令牌位来增加或减少延迟。令牌位一次移位一个位置。因此，不会发生毛刺。

8. 发明授权

US06566907B1 Unclocked digital sequencer circuit with flexibly ordered output signal edges 有权
标题翻译：未定时的数字音序器电路具有灵活有序的输出信号边沿
公开(公告)号：US06566907B1
公开(公告)日：2003-05-20
申请号：US10007285
申请日：2001-11-08
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03K1900
CPC分类号： H03K5/133 , G06F1/025
摘要： An unclocked, digital sequencer circuit having flexibly ordered leading and trailing edges on the output signals. The sequencer circuit of the invention includes a dual-input latch that detects only leading edges on a first input terminal and only trailing edges on a second input terminal. A delay line provides successively delayed input signals. Two delayed input signals are coupled to the first and second input terminals of each of two or more dual-input latches that provide a set of sequencer output signals. The sequence of the output signal edges depends on which delayed input signals are selected to drive each dual-input latch. In one embodiment, the selection of delayed input signals to drive the first and second input terminals of the dual-input latches is programmable. Thus, the sequence of the leading edges on the output signals is programmable, and the sequence of the trailing edges is independently programmable.
摘要翻译：一个非锁定的数字序列器电路，其输出信号具有灵活的前沿和后沿。本发明的定序器电路包括双输入锁存器，其仅检测第一输入端子上的前沿，仅检测第二输入端子的后沿。延迟线提供相继延迟的输入信号。两个延迟的输入信号耦合到提供一组定序器输出信号的两个或多个双输入锁存器中的每一个的第一和第二输入端子。输出信号边沿的顺序取决于选择延迟的输入信号来驱动每个双输入锁存器。在一个实施例中，用于驱动双输入锁存器的第一和第二输入端的延迟输入信号的选择是可编程的。因此，输出信号上的前沿的顺序是可编程的，并且后沿的顺序是独立可编程的。

9. 发明授权

US06515486B1 Method and structure to determine low threshold voltage and high threshold voltage 有权
标题翻译：确定低阈值电压和高阈值电压的方法和结构
公开(公告)号：US06515486B1
公开(公告)日：2003-02-04
申请号：US09603461
申请日：2000-06-22
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： G01R2728
CPC分类号： G01R31/30
摘要： A method is provided for quickly determining low threshold voltages and high threshold voltages of a test circuit. Specifically, a transformed voltage transfer curve for the test circuit is generated. The maximum and minimum points of the transfer circuit are determined to calculate transformed voltage threshold values. The transformed voltage threshold are transformed to find the desired threshold voltages.
摘要翻译：提供了一种用于快速确定测试电路的低阈值电压和高阈值电压的方法。具体地，产生用于测试电路的变换的电压传递曲线。确定传送电路的最大和最小点以计算变换电压阈值。变换的电压阈值被变换以找到所需的阈值电压。

10. 发明授权

US06373308B1 Direct-measured DLL circuit and method 有权
标题翻译：直接测量DLL电路和方法
公开(公告)号：US06373308B1
公开(公告)日：2002-04-16
申请号：US09755671
申请日：2001-01-05
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03L700
CPC分类号： H03K5/00006 , H03K5/131 , H03K5/133 , H03L7/0814 , H03L7/085
摘要： A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. A single synchronization step is sufficient, provided that the frequency of the input clock signal is stable. Further, only one delay line is required to implement the DLL circuit. Therefore, the DLL of the present invention is both quick to “lock in” a clock signal and efficient in the use of hardware resources. Further, the present DLL is very accurate, because the same delay line is used to calculate the necessary additional delay and to generate the output clock signal.
摘要翻译：延迟锁定环路（DLL）电路和方法，接受输入时钟信号和反馈时钟信号，并提供必要的附加延迟，使反馈时钟信号与输入时钟信号同步。只要输入时钟信号的频率稳定，单个同步步骤就足够了。此外，仅需要一条延迟线来实现DLL电路。因此，本发明的DLL既快速地“锁定”时钟信号并且有效地使用硬件资源。此外，本DLL非常精确，因为使用相同的延迟线来计算必要的附加延迟并产生输出时钟信号。

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