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1. 发明申请

US20130149830A1 METHODS OF FORMING FIELD EFFECT TRANSISTORS HAVING SILICON-GERMANIUM SOURCE/DRAIN REGIONS THEREIN 审中-公开
标题翻译：形成具有硅锗源/漏区的场效应晶体管的方法
公开(公告)号：US20130149830A1
公开(公告)日：2013-06-13
申请号：US13313881
申请日：2011-12-07
申请人： Hwa-Sung RHEE , Seung-Chul Lee , Chul-Wan An , Henry K. Utomo , Seong-Dong Kim
发明人： Hwa-Sung RHEE , Seung-Chul Lee , Chul-Wan An , Henry K. Utomo , Seong-Dong Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L29/0649 , H01L29/165 , H01L29/41766 , H01L29/456 , H01L29/66477 , H01L29/6656 , H01L29/66636 , H01L29/7834 , H01L29/7845 , H01L29/7848
摘要： Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches. Silicon germanium (SiGe) source and drain regions may be formed using an epitaxial growth process. During this growth process, the bottoms and sidewalls of the trenches may be used as “seeds” for the silicon germanium growth. An epitaxial growth step may then be performed to define silicon capping layers on the SiGe source and drain regions.
摘要翻译：形成场效应晶体管的方法包括使用栅电极作为蚀刻掩模来选择性地将源极和漏极区沟槽刻蚀成半导体区域。执行外延生长工艺以填充源极和漏极区沟槽。可以使用外延生长工艺来形成硅锗（SiGe）源极和漏极区。在该生长过程中，沟槽的底部和侧壁可以用作硅锗生长的“种子”。然后可以执行外延生长步骤以在SiGe源极和漏极区上限定硅覆盖层。

2. 发明授权

US08138053B2 Method of forming source and drain of field-effect-transistor and structure thereof 失效
标题翻译：形成场效应晶体管的源极和漏极的方法及其结构
公开(公告)号：US08138053B2
公开(公告)日：2012-03-20
申请号：US11763561
申请日：2007-06-15
申请人： Henry K. Utomo , Shailendra Mishra , Lee Wee Teo , Jae Gon Lee , Shyue Seng Tan
发明人： Henry K. Utomo , Shailendra Mishra , Lee Wee Teo , Jae Gon Lee , Shyue Seng Tan
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.
摘要翻译：本发明的实施例提供了形成场效应晶体管（FET）的方法。该方法包括：注入一个或多个n型掺杂剂以产生一个或多个注入区，其中至少一部分注入区被指定为用于形成FET的源极和漏极扩展的区域; 激活植入区域; 用氯气蚀刻剂蚀刻以在注入区域中形成开口，以及通过在开口中外延生长嵌入式硅锗形成源极和漏极延伸部分。还提供了由其制成的半导体场效应晶体管的结构。

3. 发明申请

US20090029531A1 HYBRID ORIENTATION SUBSTRATE AND METHOD FOR FABRICATION THEREOF 有权
标题翻译：混合方向衬底及其制造方法
公开(公告)号：US20090029531A1
公开(公告)日：2009-01-29
申请号：US12244944
申请日：2008-10-03
申请人： Haining S. Yang , Henry K. Utomo , Judson R. Holt
发明人： Haining S. Yang , Henry K. Utomo , Judson R. Holt
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L21/26533 , H01L21/823807 , H01L27/1203 , H01L29/045
摘要： A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.
摘要翻译：一种混合取向基片的制造方法，其特征在于：（1）使基底半导体衬底的一部分露出的被掩膜的表面半导体层的水平外延增强; 和（2）基底半导体衬底的暴露部分的垂直外延增加。所得到的表面半导体层和外延表面半导体层与不与基底半导体衬底垂直的界面邻接。该方法还包括通过表面半导体层和外延表面半导体层注入电介质形成离子，以提供将表面半导体层和外延表面半导体层与基底半导体衬底分离的掩埋电介质层。

4. 发明授权

US07482209B2 Hybrid orientation substrate and method for fabrication of thereof 失效
标题翻译：混合取向基板及其制造方法
公开(公告)号：US07482209B2
公开(公告)日：2009-01-27
申请号：US11559151
申请日：2006-11-13
申请人： Haining S. Yang , Henry K. Utomo , Judson R. Holt
发明人： Haining S. Yang , Henry K. Utomo , Judson R. Holt
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/26533 , H01L21/823807 , H01L27/1203 , H01L29/045
摘要： A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.
摘要翻译：一种混合取向基片的制造方法，其特征在于：（1）使基底半导体衬底的一部分露出的被掩膜的表面半导体层的水平外延增强; 和（2）基底半导体衬底的暴露部分的垂直外延增加。所得到的表面半导体层和外延表面半导体层与不与基底半导体衬底垂直的界面邻接。该方法还包括通过表面半导体层和外延表面半导体层注入电介质形成离子，以提供将表面半导体层和外延表面半导体层与基底半导体衬底分离的掩埋电介质层。

5. 发明授权

US07176481B2 In situ doped embedded sige extension and source/drain for enhanced PFET performance 有权
标题翻译：用于增强PFET性能的原位掺杂嵌入式扩展和源极/漏极
公开(公告)号：US07176481B2
公开(公告)日：2007-02-13
申请号：US10905598
申请日：2005-01-12
申请人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry K. Utomo , Werner A. Rausch
发明人： Huajie Chen , Dureseti Chidambarrao , Siddhartha Panda , Sang-Hyun Oh , Henry K. Utomo , Werner A. Rausch
IPC分类号： H01L29/06
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.
摘要翻译：公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

6. 发明授权

US08685818B2 Method of forming a shallow trench isolation embedded polysilicon resistor 有权
标题翻译：形成浅沟槽隔离嵌入式多晶硅电阻器的方法
公开(公告)号：US08685818B2
公开(公告)日：2014-04-01
申请号：US12823168
申请日：2010-06-25
申请人： Huiling Shang , Ying Li , Henry K. Utomo
发明人： Huiling Shang , Ying Li , Henry K. Utomo
IPC分类号： H01L29/8605
CPC分类号： H01L28/20 , H01L21/76229 , H01L27/0629
摘要： Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants.
摘要翻译：在分离两个相邻器件的有源区域的浅沟槽隔离件之间形成多晶硅嵌入式电阻器，最小化两个器件之间的电气相互作用，并减少它们之间的电容耦合或泄漏。当多晶硅电阻器嵌入STI凹陷区域内时，通过在STI区域内形成凹陷区域，独立于形成栅电极而形成精密多晶硅电阻器。多晶硅电阻器与栅极电极分离，使其免受与栅电极相关的工艺的影响。该方法在形成STI之后但在形成p阱和n阱注入之前形成多晶硅电阻器。在另一个实施例中，在形成STI之后但在形成井注入之后形成电阻器。

7. 发明授权

US08637941B2 Self-aligned contact employing a dielectric metal oxide spacer 有权
标题翻译：使用介电金属氧化物间隔物的自对准接触
公开(公告)号：US08637941B2
公开(公告)日：2014-01-28
申请号：US12943995
申请日：2010-11-11
申请人： Ying Li , Henry K. Utomo
发明人： Ying Li , Henry K. Utomo
IPC分类号： H01L29/72
CPC分类号： H01L29/401 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76897 , H01L21/823842 , H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.
摘要翻译：电介质衬垫形成在栅叠层的侧壁上，下电触头层介质材料层沉积在电介质衬垫上并进行平面化处理。电介质衬垫相对于下接触层电介质材料层的顶表面和栅叠层的顶表面凹陷。沉积并平坦化介电金属氧化物层以形成围绕栅极堆叠的上部的电介质金属氧化物间隔物。电介质金属氧化物层具有与平坦化的下部接触电介质材料层的顶表面共面的顶表面。可选地，栅叠层中的导电材料可以被替换。在沉积至少一个上接触电介质材料层之后，使用介电金属氧化物间隔物作为自对准结构形成延伸到半导体衬底的至少一个通孔。

8. 发明申请

US20120119307A1 SELF-ALIGNED CONTACT EMPLOYING A DIELECTRIC METAL OXIDE SPACER 有权
标题翻译：自对准接触器采用介电金属氧化物间隔器
公开(公告)号：US20120119307A1
公开(公告)日：2012-05-17
申请号：US12943995
申请日：2010-11-11
申请人： Ying Li , Henry K. Utomo
发明人： Ying Li , Henry K. Utomo
IPC分类号： H01L29/772 , H01L21/283
CPC分类号： H01L29/401 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/76897 , H01L21/823842 , H01L21/823864 , H01L21/823871 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.
摘要翻译：电介质衬垫形成在栅叠层的侧壁上，下电触头层介质材料层沉积在电介质衬垫上并进行平面化处理。电介质衬垫相对于下接触电介质材料层的顶表面和栅极堆叠的顶表面凹陷。介电金属氧化物层被沉积并平坦化以形成围绕栅叠层的上部的电介质金属氧化物间隔物。电介质金属氧化物层具有与平坦化的下接触电介质材料层的顶表面共面的顶表面。可选地，可以更换栅叠层中的导电材料。在沉积至少一个上接触电介质材料层之后，使用介电金属氧化物间隔物作为自对准结构形成延伸到半导体衬底的至少一个通孔。

9. 发明申请

US20090146181A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS 审中-公开
标题翻译：采用扩散源/漏斗扩展的集成电路系统
公开(公告)号：US20090146181A1
公开(公告)日：2009-06-11
申请号：US11952939
申请日：2007-12-07
申请人： Chung Woh Lai , Oleg Gluschenkov , Henry K. Utomo , Lee Wee Teo , Jin Ping Liu , Anita Madan , Rainer Loesing , Jin-Ping Han , Hyung-Yoon Choi
发明人： Chung Woh Lai , Oleg Gluschenkov , Henry K. Utomo , Lee Wee Teo , Jin Ping Liu , Anita Madan , Rainer Loesing , Jin-Ping Han , Hyung-Yoon Choi
IPC分类号： H01L29/778 , H01L21/336 , H01L29/78
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.
摘要翻译：一种集成电路系统，包括：提供包括掺杂外延层的PFET器件; 以及通过使用能量源从掺杂的外延层扩散掺杂剂形成源极/漏极扩展。

10. 发明申请

US20080166847A1 METHOD OF FORMING SOURCE AND DRAIN OF FIELD-EFFECT-TRANSISTOR AND STRUCTURE THEREOF 失效
标题翻译：形成源和场效应晶体管的方法及其结构
公开(公告)号：US20080166847A1
公开(公告)日：2008-07-10
申请号：US11763561
申请日：2007-06-15
申请人： Henry K. Utomo , Shailendra Mishra , Lee Wee Teo , Jae Gon Lee , Shyue Seng Tan
发明人： Henry K. Utomo , Shailendra Mishra , Lee Wee Teo , Jae Gon Lee , Shyue Seng Tan
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7848
摘要： Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.
摘要翻译：本发明的实施例提供了形成场效应晶体管（FET）的方法。该方法包括：注入一个或多个n型掺杂剂以产生一个或多个注入区，其中至少一部分注入区被指定为用于形成FET的源极和漏极扩展的区域; 激活植入区域; 用氯气蚀刻剂蚀刻以在注入区域中形成开口，以及通过在开口中外延生长嵌入式硅锗形成源极和漏极延伸部分。还提供了由其制成的半导体场效应晶体管的结构。

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