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1. 发明申请

US20060035521A1 Power contact having current flow guiding feature and electrical connector containing same 有权
标题翻译：具有电流导向特征的电力接触件和包含其的电连接器
公开(公告)号：US20060035521A1
公开(公告)日：2006-02-16
申请号：US10919632
申请日：2004-08-16
申请人： Hung Ngo , Wilfred Swain
发明人： Hung Ngo , Wilfred Swain
IPC分类号： H01R13/648
CPC分类号： H01R12/7088 , H01R12/725
摘要： An electrical contact for transmitting power to a printed circuit structure. The power contact comprises a main section that includes a first edge and an opposing second edge, and is made from electrically conductive material. A current-receiving interface is disposed between the main section first and second edges. And a plurality of terminals extend from the main section along the second edge. A void of electrically conductive material is formed in the main section for guiding current flow from the current-receiving interface to the terminals.
摘要翻译：用于将电力传输到印刷电路结构的电触头。电源触点包括主要部分，其包括第一边缘和相对的第二边缘，并且由导电材料制成。电流接收接口设置在主部分第一和第二边缘之间。并且多个端子沿着第二边缘从主要部分延伸。在主部分中形成导电材料的空隙，用于引导从电流接收界面到端子的电流流动。

2. 发明申请

US20070197063A1 ELECTRICAL CONNECTORS HAVING POWER CONTACTS WITH ALIGNMENT AND/OR RESTRAINING FEATURES 有权
标题翻译：具有对准和/或限制功能的电源触点的电气连接器
公开(公告)号：US20070197063A1
公开(公告)日：2007-08-23
申请号：US11358168
申请日：2006-02-21
申请人： Hung Ngo , Wilfred Swain
发明人： Hung Ngo , Wilfred Swain
IPC分类号： H01R13/648
CPC分类号： H01R12/7088 , H01R12/724 , H01R12/727
摘要： Preferred embodiments of power contacts have alignment features that can maintain conductors of the power contacts in a state of alignment during and after insertion of the power contacts into a housing.
摘要翻译：功率触点的优选实施例具有对准特征，其可以在电力触头插入壳体期间和之后将电力触头的导体保持在对准状态。

3. 发明申请

US20060281354A1 Electrical power contacts and connectors comprising same 有权
标题翻译：电源触点和包括该电源触点的连接器
公开(公告)号：US20060281354A1
公开(公告)日：2006-12-14
申请号：US11450494
申请日：2006-06-09
申请人： Hung Ngo , Christopher Daily , Wilfred Swain , Stuart Stoner , Christopher Kolivoski , Douglas Johnescu
发明人： Hung Ngo , Christopher Daily , Wilfred Swain , Stuart Stoner , Christopher Kolivoski , Douglas Johnescu
IPC分类号： H01R13/28
CPC分类号： H01R13/28 , H01R12/7088 , H01R12/727 , H01R13/113
摘要： Preferred embodiments of power contacts include two or more opposing contact beams of a first type that are spaced apart along at least a portion of the length thereof when the power contact is in an unmated state; and two or more opposing contact beams of a second type. The contact beams of the second type are spaced apart so that the contact beams of the second type pinch the contact beams of the first type when the power contact is mated with a mating contact, thereby causing the contact beams of the first type of deflect inwardly toward each other.
摘要翻译：电力触点的优选实施例包括当电力接触处于未配合状态时沿着其长度的至少一部分间隔开的第一类型的两个或更多个相对的接触梁; 以及第二类型的两个或更多个相对的接触梁。第二类型的接触梁间隔开，使得当动力接触与配合接触件配合时，第二类型的接触梁夹住第一类型的接触梁，从而使第一类型的接触梁向内朝向对方

4. 发明申请

US20070096770A1 Cascaded pass-gate test circuit with interposed split-output drive devices 失效
标题翻译：带有插入式分离输出驱动装置的级联传输门测试电路
公开(公告)号：US20070096770A1
公开(公告)日：2007-05-03
申请号：US11260571
申请日：2005-10-27
申请人： Ching-Te Chuang , Jente Kuang , Hung Ngo
发明人： Ching-Te Chuang , Jente Kuang , Hung Ngo
IPC分类号： H03K19/00
CPC分类号： G01R31/31725
摘要： A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.
摘要翻译：包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

5. 发明申请

US20070082535A1 High Speed, High Signal Integrity Electrical Connectors 有权
标题翻译：高速，高信号完整性电气连接器
公开(公告)号：US20070082535A1
公开(公告)日：2007-04-12
申请号：US11608433
申请日：2006-12-08
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： H01R13/627
CPC分类号： H01R13/6658 , H01R12/721 , H01R13/514 , H01R13/516 , H01R13/6215
摘要： An electrical connector may include a connector housing and a terminal tray. The terminal tray may include a tray body having a latch extending therefrom. The connector housing may define a latch receiving window. The latch and latch receiving window may be disposed such that the latch engages the latch receiving window only when the terminal tray is received in the housing in a preferred orientation. The terminal tray may include an electrically conductive contact having a board receiving end adapted to receive a printed circuit board and to exert sufficient pressure on the printed circuit board to retain the printed circuit board between the contact and the tray body. The connector may also include a plurality of cables bundled by a band, such as double-sided tape, such that respective portions of the cables are restrained from movement relative to one another.
摘要翻译：电连接器可以包括连接器壳体和端子托盘。端子盘可以包括具有从其延伸的闩锁的托盘主体。连接器壳体可以限定闩锁接收窗口。闩锁和闩锁接收窗口可以被布置成使得仅当终端托盘以优选的方向容纳在壳体中时，闩锁接合闩锁接收窗口。端子托盘可以包括导电触点，其具有适于接收印刷电路板的板接收端并且在印刷电路板上施加足够的压力以将印刷电路板保持在接触件和托盘主体之间。连接器还可以包括由诸如双面胶带的带捆绑的多个电缆，使得电缆的相应部分被限制为相对于彼此移动。

6. 发明申请

US20070061126A1 System for and method of emulating electronic input devices 审中-公开
标题翻译：仿真电子输入设备的系统和方法
公开(公告)号：US20070061126A1
公开(公告)日：2007-03-15
申请号：US11219100
申请日：2005-09-01
申请人： Anthony Russo , Frank Chen , Mark Howell , Hung Ngo , Marcia Tsuchiya , David Weigand
发明人： Anthony Russo , Frank Chen , Mark Howell , Hung Ngo , Marcia Tsuchiya , David Weigand
IPC分类号： G06F9/455
CPC分类号： G06F3/03547 , G06F3/04883
摘要： The system and method of the present invention is directed to emulating and configuring any of a plurality of electronic input devices. A system in accordance with one embodiment of the present invention comprises an interface and an emulator. The interface is for selecting and configuring an electronic input device from a plurality of electronic input devices, and the emulator is for emulating the electronic input device. Preferably, the plurality of electronic input devices comprise any two or more of a scroll wheel, a mouse, a joy stick, a steering wheel, an analog button, and a touch bar. Also in a preferred embodiment, the interface is an Application Programming Interface (API) and the emulator comprises a finger swipe sensor for receiving user input.
摘要翻译：本发明的系统和方法旨在仿真和配置多个电子输入设备中的任何一个。根据本发明的一个实施例的系统包括接口和仿真器。该接口用于从多个电子输入设备中选择和配置电子输入设备，并且该仿真器用于仿真电子输入设备。优选地，多个电子输入装置包括滚轮，鼠标，操纵杆，方向盘，模拟按钮和触摸条中的任何两个或更多个。同样在优选实施例中，接口是应用编程接口（API），并且仿真器包括用于接收用户输入的手指滑动传感器。

7. 发明申请

US20060103441A1 Digital duty cycle corrector 失效
标题翻译：数字占空比校正器
公开(公告)号：US20060103441A1
公开(公告)日：2006-05-18
申请号：US10988454
申请日：2004-11-12
申请人： Gary Carpenter , Alan Drake , Fadi Gebara , Chandler McDowell , Hung Ngo
发明人： Gary Carpenter , Alan Drake , Fadi Gebara , Chandler McDowell , Hung Ngo
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.
摘要翻译：公开了一种校正数字信号占空比的电路和方法。测量输入数字信号的占空比并将其与期望的占空比进行比较。输入数字信号的前沿被传递到输出。该电路和方法调节输出端的下降沿以达到所需的占空比。响应于延迟版本的输入数字信号的上升沿发生下降沿。

8. 发明申请

US20060103431A1 Dynamic logic circuit incorporating reduced leakage state-retaining devices 失效
标题翻译：动态逻辑电路结合了减少的泄漏状态保持装置
公开(公告)号：US20060103431A1
公开(公告)日：2006-05-18
申请号：US10992486
申请日：2004-11-18
申请人： Hung Ngo , Jente Kuang , Harmander Deogun , AJ Kleinosowski
发明人： Hung Ngo , Jente Kuang , Harmander Deogun , AJ Kleinosowski
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , H03K19/0016
摘要： A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.
摘要翻译：结合减少泄漏状态保持装置的动态逻辑电路降低了处理器和其他结合动态电路的系统的功耗。保持器电路提供动态电路的输出级的状态的低泄漏保持，使得输出电路脚装置可以被禁用，除非在动态电路的输出中需要转换。保持器电路包括具有比输出电路中的对应晶体管更小的面积的晶体管，从而当保持器电路保持输出并且输出电路脚器件被禁用时减小通过输出电路的栅极的泄漏。可以通过延迟版本的动态逻辑门输出来提供输出电路脚装置的自定时控制，或者可以由产生预充电时钟的延迟版本或多周期信号的外部控制电路提供。

9. 发明申请

US20050110581A1 PHASE CLOCK SELECTOR FOR GENERATING A NON-INTEGER FREQUENCY DIVISION 失效
标题翻译：用于生成非整数频率部分的相位选择器
公开(公告)号：US20050110581A1
公开(公告)日：2005-05-26
申请号：US10718063
申请日：2003-11-20
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： G04G3/02 , H03K23/66 , H03K23/68 , H03L7/099 , H03L7/197 , G04B21/00 , G04C21/00 , H03L7/00
CPC分类号： H03L7/1974 , G04G3/02 , H03K23/667 , H03K23/68 , H03L7/0996
摘要： A frequency divider circuit uses a base counter to frequency divide a clock signal with period T by an integer value N and employs a cyclic rotational select circuit to select among multiple equally phase shifted signals of a multiple phase clock to generate a fractional term P/k where P is variable from 0 to k−1. The counter counts an output clock that corresponds to the output of a multiplexer selecting from among the multiple clock phases. Depending on the desired fractional term, after N counts of the output clock phases of the multiple phase clock are selected glitch free by rotationally selecting a first phase, and skipping either 0, 1, 2 . . . up to k−1 sequential phases to generate fractional terms 0, 1/k, 2/k, 3/k . . . k−1/k, respectively, thus providing frequency division corresponding to N+P/k where P may be varied from 0 to k−1.
摘要翻译：分频器电路使用基本计数器对具有周期T的时钟信号进行频率分频整数N，并且采用循环旋转选择电路在多相等时相位信号中选择多个相位时钟以产生分数项P / k 其中P从0到k-1是可变的。计数器对与多个时钟相位中选择的多路复用器的输出相对应的输出时钟进行计数。根据期望的分数项，通过旋转选择第一相位，并跳过0,1,2，多次相位时钟的输出时钟相位的N个计数被无毛刺选择。。。直到k-1个顺序相位来产生分数项0,1 / k，2 / k，3 / k。。。 k-1 / k，从而提供对应于N + P / k的频分，其中P可以从0到k-1变化。

10. 发明申请

US20050102345A1 4-to-2 carry save adder using limited switching dynamic logic 失效
标题翻译：使用有限切换动态逻辑的4对2进位保存加法器
公开(公告)号：US20050102345A1
公开(公告)日：2005-05-12
申请号：US10702989
申请日：2003-11-06
申请人： Wendy Belluomini , Ramyanshu Datta , Chandler McDowell , Robert Montoye , Hung Ngo
发明人： Wendy Belluomini , Ramyanshu Datta , Chandler McDowell , Robert Montoye , Hung Ngo
IPC分类号： G06F7/50 , G06F7/60
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.
摘要翻译：一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。

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