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1. 发明申请

US20060103441A1 Digital duty cycle corrector 失效
标题翻译：数字占空比校正器
公开(公告)号：US20060103441A1
公开(公告)日：2006-05-18
申请号：US10988454
申请日：2004-11-12
申请人： Gary Carpenter , Alan Drake , Fadi Gebara , Chandler McDowell , Hung Ngo
发明人： Gary Carpenter , Alan Drake , Fadi Gebara , Chandler McDowell , Hung Ngo
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.
摘要翻译：公开了一种校正数字信号占空比的电路和方法。测量输入数字信号的占空比并将其与期望的占空比进行比较。输入数字信号的前沿被传递到输出。该电路和方法调节输出端的下降沿以达到所需的占空比。响应于延迟版本的输入数字信号的上升沿发生下降沿。

2. 发明申请

US20070096782A1 Method and apparatus for fail-safe and restartable system clock generation 失效
标题翻译：用于故障安全和可重启系统时钟生成的方法和装置
公开(公告)号：US20070096782A1
公开(公告)日：2007-05-03
申请号：US11260563
申请日：2005-10-27
申请人： Hung Ngo , Gary Carpenter , Fadi Gebara , Jente Kuang
发明人： Hung Ngo , Gary Carpenter , Fadi Gebara , Jente Kuang
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , G06F1/04
摘要： A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.
摘要翻译：用于故障安全和可重新启动的系统时钟生成的方法和装置提供了由于错误的时钟发生器设置或边缘时钟分配组件导致的故障的恢复。在时钟发生器的输出与下游电路之间的时钟分配路径的某一点检测到时钟故障。如果检测到时钟故障，则可以使用可能是时钟发生器参考时钟的第二时钟来操作下游电路。时钟发生器可以是锁相环，然后重新启动下游电路被保证工作的预定环路滤波器电压，或者在时钟发生器的输出端上分频器设置，从而降低频率确保下游电路工作。因此，时钟发生器的参数可以在将时钟发生器的输出恢复到下行电路之前被确定并且确定操作条件。

3. 发明申请

US20070018737A1 High frequency ring oscillator with feed-forward paths 失效
标题翻译：具有前馈路径的高频环形振荡器
公开(公告)号：US20070018737A1
公开(公告)日：2007-01-25
申请号：US11184352
申请日：2005-07-19
申请人： Alan Drake , Fadi Gebara , Jeremy Schaub
发明人： Alan Drake , Fadi Gebara , Jeremy Schaub
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K3/012
摘要： An inverting circuit comprises a first inverter in a main path having a first input and a common ouput. A second inverter receives the first input and is coupled with a first voltage controlled pass gate to the common output. A third inverter couples a second input to the common output using a second voltage controlled pass gate. A fourth inverter couples the second input to the common output using the first voltage controlled pass gate. A ring oscillator is formed using a number N of the inverting circuits with each common output coupled to the first inputs forming a main ring of a ring oscillator. The second inputs are coupled to feed-forward signals from selected outputs. The resulting signals at the common outputs are an interpolation of the first and second input signals modulated by a control voltage coupled to the first and second pass gates.
摘要翻译：反相电路包括具有第一输入和公共输出的主路径中的第一反相器。第二反相器接收第一输入并与第一电压控制的通过门耦合到公共输出端。第三反相器使用第二电压控制通孔将第二输入耦合到公共输出。第四反相器使用第一电压控制通路将第二输入耦合到公共输出端。使用数目为N的反相电路形成环形振荡器，其中每个公共输出耦合到形成环形振荡器的主环的第一输入。第二输入耦合到来自所选输出的前馈信号。在公共输出端产生的信号是由耦合到第一和第二通道门的控制电压调制的第一和第二输入信号的内插。

4. 发明申请

US20080024233A1 High Frequency Ring Oscillator With Feed-Forward Paths 审中-公开
标题翻译：具有前馈路径的高频环形振荡器
公开(公告)号：US20080024233A1
公开(公告)日：2008-01-31
申请号：US11849844
申请日：2007-09-04
申请人： Alan Drake , Fadi Gebara , Jeremy Schaub
发明人： Alan Drake , Fadi Gebara , Jeremy Schaub
IPC分类号： H03K3/03 , H03L7/00
CPC分类号： H03K3/0315 , H03K3/012
摘要： An inverting circuit comprises a first inverter in a main path having a first input and a common ouput. A second inverter receives the first input and is coupled with a first voltage controlled pass gate to the common output. A third inverter couples a second input to the common output using a second voltage controlled pass gate. A fourth inverter couples the second input to the common output using the first voltage controlled pass gate. A ring oscillator is formed using a number N of the inverting circuits with each common output coupled to the first inputs forming a main ring of a ring oscillator. The second inputs are coupled to feed-forward signals from selected outputs. The resulting signals at the common outputs are an interpolation of the first and second input signals modulated by a control voltage coupled to the first and second pass gates.
摘要翻译：反相电路包括具有第一输入和公共输出的主路径中的第一反相器。第二反相器接收第一输入并与第一电压控制的通过门耦合到公共输出端。第三反相器使用第二电压控制通孔将第二输入耦合到公共输出。第四反相器使用第一电压控制通路将第二输入耦合到公共输出端。使用数目为N的反相电路形成环形振荡器，其中每个公共输出耦合到形成环形振荡器的主环的第一输入。第二输入耦合到来自所选输出的前馈信号。在公共输出端产生的信号是由耦合到第一和第二通道门的控制电压调制的第一和第二输入信号的内插。

5. 发明申请

US20060103478A1 Ultra high frequency ring oscillator with voltage controlled frequency capabilities 失效
公开(公告)号：US20060103478A1
公开(公告)日：2006-05-18
申请号：US10988463
申请日：2004-11-12
申请人： Richard Brown , Gary Carpenter , Fadi Gebara
发明人： Richard Brown , Gary Carpenter , Fadi Gebara
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , H03K3/356139 , H03K5/133 , H03L7/0995
摘要： A pseudo Set/Reset latch circuit is configured with modified NOR or NAND gates wherein one of the series pull-up devices or pull-down devices is removed. A minimum of three pseudo Set/Reset latches may be coupled as a ring oscillator generating an output and a non-skewed complementary output. Additionally, feed-forward inverting stages may be coupled in parallel with inverting paths in the ring oscillator primary path to further increase the frequency range of the ring oscillator. The pseudo Set/Reset latch circuits and the feed-forward inverting stages may be configured with voltage controlled devices that alter the delay of the stages as a means for varying the frequency of the ring oscillator either by varying the current drive of the circuitry driving the output of the latch stages or by varying the conductance of devices coupling between the latch stages. Feedforward inverting stages may comprise pseudo latches or inverter gates.

6. 发明申请

US20070164769A1 Active cancellation matrix for process parameter measurements 失效
标题翻译：用于过程参数测量的主动消除矩阵
公开(公告)号：US20070164769A1
公开(公告)日：2007-07-19
申请号：US11333612
申请日：2006-01-17
申请人： Fadi Gebara , Ying Liu , Jayakumaran Sivagnaname , Ivan Vo
发明人： Fadi Gebara , Ying Liu , Jayakumaran Sivagnaname , Ivan Vo
IPC分类号： G01R31/26
CPC分类号： G11C29/50 , G01R31/3004 , G11C2029/5002 , G11C2029/5006
摘要： An active cancellation matrix for process parameter measurements provides feedback paths for each test location wherein each feedback path is used to sense the applied voltage and the sensed voltage is used to adjust the source voltage for any variations along the input path. The devices under test are arranged in a row and column array, and the feedback and voltage input paths are formed along respective rails which extend generally parallel to a row of devices under test. Selectors are used to selectively route the outputs of the test nodes to a measurement unit such as a current sensor. The input voltages can be varied to establish current-voltage (I-V) curves for the devices under various conditions. In the example where the devices under test are transistors, each source input includes three voltage inputs (rails) for a drain voltage, a source voltage, and a gate voltage.
摘要翻译：用于过程参数测量的主动消除矩阵为每个测试位置提供反馈路径，其中每个反馈路径用于感测所施加的电压，并且所感测的电压用于调整沿着输入路径的任何变化的源电压。被测设备被布置成行和列阵列，并且反馈和电压输入路径沿着相应的轨道形成，该轨道大致平行于被测试的器件的一排。选择器用于选择性地将测试节点的输出路由到诸如电流传感器的测量单元。可以改变输入电压以在各种条件下为器件建立电流 - 电压（I-V）曲线。在被测器件为晶体管的示例中，每个源极输入包括用于漏极电压，源极电压和栅极电压的三个电压输入（导线）。

7. 发明申请

US20070244656A1 METHOD AND APPARATUS FOR DETERMINING JITTER AND PULSE WIDTH FROM CLOCK SIGNAL COMPARISONS 失效
标题翻译：用于确定时钟信号比较的抖动和脉冲宽度的方法和装置
公开(公告)号：US20070244656A1
公开(公告)日：2007-10-18
申请号：US11279651
申请日：2006-04-13
申请人： Hayden Cranford , Fadi Gebara , Jeremy Schaub
发明人： Hayden Cranford , Fadi Gebara , Jeremy Schaub
IPC分类号： G06F19/00 , G01R29/02 , G06F17/40
CPC分类号： G01R31/31709 , G01R31/31725
摘要： A method and apparatus for determining jitter and pulse width from clock signal comparisons provides a low cost and production-integrable mechanism for measuring a clock signal with a reference clock, both of unknown frequency. The measured clock signal is sampled at transitions of a reference clock and the sampled values are collected in a histogram according to a folding of the samples around a timebase which is either swept to detect a minimum jitter for the folded data or is obtained from direct frequency analysis for the sample set. The histogram for the correct estimated period is statistically analyzed to yield the pulse width, which is the difference between the peaks of the probability density function and jitter, which corresponds to width of the density function peaks. Frequency drift is corrected by adjusting the timebase used to fold the data across the sample set.
摘要翻译：用于从时钟信号比较确定抖动和脉冲宽度的方法和装置提供了一种低成本和可生产可集成的机制，用于测量具有未知频率的参考时钟的时钟信号。测量的时钟信号在参考时钟的转变时被采样，并且采样值被收集在直方图中，根据时基的周围样本的折叠，该时基被扫描以检测折叠数据的最小抖动，或者从直接频率获得分析样本集。统计分析正确估计周期的直方图以产生脉冲宽度，其是概率密度函数和抖动的峰值之间的差异，其对应于密度函数峰值的宽度。通过调整用于将样本集合中的数据折叠的时基来校正频率漂移。

8. 发明申请

US20060103445A1 Method and apparatus for generating non-skewed complementary signals through interpolation 失效
公开(公告)号：US20060103445A1
公开(公告)日：2006-05-18
申请号：US10988455
申请日：2004-11-12
申请人： Juan-antonio Carballo , Fadi Gebara
发明人： Juan-antonio Carballo , Fadi Gebara
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , H03K5/1515
摘要： A complementary digital signal generator circuit and method receives a periodic digital signal, such as a square wave, as an input and generates at the output complementary versions of the digital signal delayed by matching increments of delay with minimum skew at GHz frequencies. The digital signal is processed by inverters and interpolators which may be readily matched in size and functional characteristics by close proximity placement on integrated circuits. An inverted and first delayed version of the original digital signal is applied to both inputs of a first interpolator, to generate at the output of the interpolator the complement of the digital signal as delayed by the first delayed and the delay introduced by the interpolator. The inverted and first delayed digital signal is inverted and second delayed by a second matching inverter and applied as one input to a second interpolator. The second input of the second interpolator is the original digital signal. The output of the second interpolator is the digital signal delayed by a corresponding combination of the first delay and the delay introduced by the second interpolator. When the first and second interpolators are matched, in the manner of the first and second inverters, the two interpolator outputs provide the digital signal and its complement with substantially no skew and matching increments of delay.

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