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1. 发明申请

US20050102345A1 4-to-2 carry save adder using limited switching dynamic logic 失效
标题翻译：使用有限切换动态逻辑的4对2进位保存加法器
公开(公告)号：US20050102345A1
公开(公告)日：2005-05-12
申请号：US10702989
申请日：2003-11-06
申请人： Wendy Belluomini , Ramyanshu Datta , Chandler McDowell , Robert Montoye , Hung Ngo
发明人： Wendy Belluomini , Ramyanshu Datta , Chandler McDowell , Robert Montoye , Hung Ngo
IPC分类号： G06F7/50 , G06F7/60
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.
摘要翻译：一个4对2进位保存加法器使用限制切换动态逻辑（LSDL）来减少功耗，同时减少输出和和传送位的延迟。 4对2进位存储加法器可以包括被配置为输出和位的第一LSDL电路。进位保存加法器还可以包括被配置为输出进位位的第二LSDL电路。第一LSDL电路和第二LSDL电路均使用先前在先前产生的当前阶段中生成的进位（下一个低位位置）。由于进位在当前阶段而不是在前一阶段中产生，所以减少输出和和进位的延迟，从而提高进位保存加法器的性能。此外，由于在进位保存加法器中使用LSDL电路，所以在使用少量的区域时功耗降低。

2. 发明申请

US20050102346A1 Computing carry-in bit to most significant bit carry save adder in current stage 失效
标题翻译：计算进位位到当前阶段的最高有效位进位保存加法器
公开(公告)号：US20050102346A1
公开(公告)日：2005-05-12
申请号：US10702992
申请日：2003-11-06
申请人： Wendy Belluomini , Ramyanshu Datta , Jente Kuang , Chandler McDowell , Robert Montoye , Hung Ngo
发明人： Wendy Belluomini , Ramyanshu Datta , Jente Kuang , Chandler McDowell , Robert Montoye , Hung Ngo
IPC分类号： G06F7/50 , G06F7/60
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.
摘要翻译：一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位前一阶段通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟由高阶全加器。

3. 发明申请

US20050071717A1 Method and apparatus for low overhead circuit scan 失效
标题翻译：低开销电路扫描的方法和装置
公开(公告)号：US20050071717A1
公开(公告)日：2005-03-31
申请号：US10670832
申请日：2003-09-25
申请人： Wendy Belluomini , Andrew Martin , Chandler McDowell , Robert Montoye
发明人： Wendy Belluomini , Andrew Martin , Chandler McDowell , Robert Montoye
IPC分类号： G01R31/3185 , G11C29/00 , G01R31/28
CPC分类号： G01R31/318572 , G11C29/003
摘要： A method and system for manipulating data in a state holding elements array. Process data is moved through the state holding elements array by a process controller. A separate scan controller scans data out of the state holding elements array by scanning data out of a group of cascaded latches where there are insufficient extra state holding elements in the group to enable normal scan. A multiplicity of local scan clocks are utilized to shift selected amounts of data only when a next state holding element in the group has been made available by clearing the contents of that next state holding element. In this way, any given latch, for the purpose of scan, is not a dedicated master or slave latch, but can act as either. This invention also addresses a circuit for the creation of the multiplicity of local clocks from a conventional LSSD clock source.
摘要翻译：用于在保持元素数组的状态下操作数据的方法和系统。过程控制器将过程数据移动通过状态保持元素数组。单独的扫描控制器通过从组中不充足的额外状态保持元件的一组级联锁存器扫描数据来扫描状态保持元件阵列中的数据，以启用正常扫描。仅当通过清除该下一状态保持元件的内容已经使该组中的下一状态保持元件可用时，才使用多个本地扫描时钟来移位所选择的数据量。以这种方式，为了扫描的目的，任何给定的锁存器不是专用的主器件或从器件锁存器，而是可以作为任一个。本发明还涉及用于从常规LSSD时钟源产生多个本地时钟的电路。

4. 发明申请

US20050195042A1 Method and ring oscillator circuit for measuring circuit delays over a wide operating range 失效
标题翻译：用于在宽工作范围内测量电路延迟的方法和环形振荡器电路
公开(公告)号：US20050195042A1
公开(公告)日：2005-09-08
申请号：US10793460
申请日：2004-03-04
申请人： Wendy Belluomini , Andrew Martin , Chandler McDowell
发明人： Wendy Belluomini , Andrew Martin , Chandler McDowell
IPC分类号： H03B1/00
CPC分类号： H03K3/0315 , G01R31/31725
摘要： A method and ring oscillator circuit for measuring circuit delays over a wide operating range permits improved analysis of dynamic circuits. A pulse generator circuit provides a pulse to an input of a dynamic circuit under test, which may be a pre-charge or evaluation pulse that is triggered by a transition of an output of the dynamic circuit that occurs during the state opposite that of the state commanded by the pulse. The action of the circuit provides for measuring any amount of delay to the next transition in the opposite state irrespective of the pulse width. By providing a wide-range of operation, characteristics such as leakage, charge sharing, data dependent node capacitance, previous value dependence as well as other dynamic circuit behaviors may be determined. The ring oscillator circuit includes an enable start circuit that causes a first pulse to be generated by the one-shot when the ring oscillator circuit is enabled.
摘要翻译：用于在宽工作范围内测量电路延迟的方法和环形振荡器电路允许改进动态电路的分析。脉冲发生器电路向待测动态电路的输入端提供脉冲，该脉冲可以是在与状态相反的状态期间发生的动态电路的输出的转变触发的预充电或评估脉冲由脉冲命令。该电路的作用提供了在相反状态下测量下一个转换的任何延迟量，而与脉冲宽度无关。通过提供广泛的操作，可以确定泄漏，电荷共享，数据相关节点电容，先前值依赖性以及其他动态电路行为等特征。环形振荡器电路包括使能启动电路，当使能环形振荡器电路时，使能起始电路通过单次触发产生第一脉冲。

5. 发明申请

US20060103441A1 Digital duty cycle corrector 失效
标题翻译：数字占空比校正器
公开(公告)号：US20060103441A1
公开(公告)日：2006-05-18
申请号：US10988454
申请日：2004-11-12
申请人： Gary Carpenter , Alan Drake , Fadi Gebara , Chandler McDowell , Hung Ngo
发明人： Gary Carpenter , Alan Drake , Fadi Gebara , Chandler McDowell , Hung Ngo
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.
摘要翻译：公开了一种校正数字信号占空比的电路和方法。测量输入数字信号的占空比并将其与期望的占空比进行比较。输入数字信号的前沿被传递到输出。该电路和方法调节输出端的下降沿以达到所需的占空比。响应于延迟版本的输入数字信号的上升沿发生下降沿。

6. 发明申请

US20060020863A1 Scanning latches using selecting array 失效
标题翻译：使用选择阵列扫描锁存器
公开(公告)号：US20060020863A1
公开(公告)日：2006-01-26
申请号：US10896505
申请日：2004-07-22
申请人： Andrew Martin , Chandler McDowell , Robert Montoye , Jun Sawada
发明人： Andrew Martin , Chandler McDowell , Robert Montoye , Jun Sawada
IPC分类号： G01R31/28
CPC分类号： G11C29/32 , G01R31/318572 , G11C11/41 , G11C2029/3202
摘要： A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of the latch can be selectively read or written to.
摘要翻译：一种用于从锁存器的矩阵阵列中的特定锁存器扫描数据的方法和系统。矩阵阵列由垂直选择线和水平数据线组成。每个锁存器通过晶体管耦合在选择器线和数据线的交叉点处。通过接通晶体管，可以选择性地读取或写入锁存器的内容。

7. 发明申请

US20080079448A1 ENHANCED SIGNAL OBSERVABILITY FOR CIRCUIT ANALYSIS 有权
标题翻译：电路分析的增强信号可视性
公开(公告)号：US20080079448A1
公开(公告)日：2008-04-03
申请号：US11949325
申请日：2007-12-03
申请人： Chandler McDowell , Stanislav Polonsky , Peilin Song , Franco Stellari , Alan Weger
发明人： Chandler McDowell , Stanislav Polonsky , Peilin Song , Franco Stellari , Alan Weger
IPC分类号： G01R31/303
CPC分类号： G01R31/311
摘要： Methods and arrangements to enhance photon emissions responsive to a signal within an integrated circuit (IC) for observability of signal states utilizing, e.g., picosecond imaging circuit analysis (PICA), are disclosed. Embodiments attach a beacon to the signal of interest and apply a voltage across the beacon to enhance photon emissions responsive to the signal of interest. The voltage is greater than the operable circuit voltage, Vd, the enhance photon emissions with respect to intensity and energy. Thus, the photon emissions are more distinguishable from noise. In many embodiments, the beacon includes a transistor and, in several embodiments, the beacon includes an enablement device to enable and disable photon emissions from the beacon. Further, a PICA detector may capture photon emissions from the beacon and process the photons to generate time traces.
摘要翻译：公开了利用例如皮秒成像电路分析（PICA）来增强响应于集成电路（IC）内的信号的信号状态的可观察性的光子发射的方法和装置。实施例将信标连接到感兴趣的信号，并在信标之间施加电压以增强响应于感兴趣的信号的光子发射。电压大于可操作电路电压Vd，相对于强度和能量增强光子发射。因此，光子发射与噪声更为区别。在许多实施例中，信标包括晶体管，并且在几个实施例中，信标包括启用和禁用来自信标的光子发射的启用装置。此外，PICA检测器可以捕获来自信标的光子发射并处理光子以产生时间迹线。

8. 发明申请

US20060028219A1 Enhanced signal observability for circuit analysis 有权
标题翻译：电路分析增强的信号可观测性
公开(公告)号：US20060028219A1
公开(公告)日：2006-02-09
申请号：US10912493
申请日：2004-08-05
申请人： Chandler McDowell , Stanislav Polonsky , Peilin Song , Franco Stellari , Alan Weger
发明人： Chandler McDowell , Stanislav Polonsky , Peilin Song , Franco Stellari , Alan Weger
IPC分类号： G01R31/28 , G06K9/00
CPC分类号： G01R31/311
摘要： Methods and arrangements to enhance photon emissions responsive to a signal within an integrated circuit (IC) for observability of signal states utilizing, e.g., picosecond imaging circuit analysis (PICA), are disclosed. Embodiments attach a beacon to the signal of interest and apply a voltage across the beacon to enhance photon emissions responsive to the signal of interest. The voltage is greater than the operable circuit voltage, Vdd, to enhance photon emissions with respect to intensity and energy. Thus, the photon emissions are more distinguishable from noise. In many embodiments, the beacon includes a transistor and, in several embodiments, the beacon includes an enablement device to enable and disable photon emissions from the beacon. Further, a PICA detector may capture photon emissions from the beacon and process the photons to generate time traces.
摘要翻译：公开了利用例如皮秒成像电路分析（PICA）来增强响应于集成电路（IC）内的信号的信号状态的可观察性的光子发射的方法和装置。实施例将信标连接到感兴趣的信号，并在信标之间施加电压以增强响应于感兴趣的信号的光子发射。电压大于可操作电路电压Vdd，以增强相对于强度和能量的光子发射。因此，光子发射与噪声更为区别。在许多实施例中，信标包括晶体管，并且在几个实施例中，信标包括启用和禁用来自信标的光子发射的启用装置。此外，PICA检测器可以捕获来自信标的光子发射并处理光子以产生时间迹线。

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