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1. 发明申请

US20100295009A1 Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane 有权
标题翻译：具有垂直通道访问晶体管和存储器平面的相变存储单元
公开(公告)号：US20100295009A1
公开(公告)日：2010-11-25
申请号：US12471287
申请日：2009-05-22
申请人： Hsiang-Lan Lung , Chung H. Lam , Ming-Hsiu Lee , Bipin Rajendran
发明人： Hsiang-Lan Lung , Chung H. Lam , Ming-Hsiu Lee , Bipin Rajendran
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的对应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻多行字线中的字线。相应的字线用作场效应晶体管的栅极。电介质将对应的字线与沟道区分开。存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

2. 发明授权

US08350316B2 Phase change memory cells having vertical channel access transistor and memory plane 有权
标题翻译：具有垂直通道存取晶体管和存储器平面的相变存储单元
公开(公告)号：US08350316B2
公开(公告)日：2013-01-08
申请号：US12471287
申请日：2009-05-22
申请人： Hsiang-Lan Lung , Chung Hon Lam , Ming-Hsiu Lee , Bipin Rajendran
发明人： Hsiang-Lan Lung , Chung Hon Lam , Ming-Hsiu Lee , Bipin Rajendran
IPC分类号： H01L29/732
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的相应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻多行字线中的字线。相应的字线用作场效应晶体管的栅极。电介质将对应的字线与沟道区分开。存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

3. 发明申请

US20100328995A1 METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY 有权
标题翻译：减少相变记忆中缺陷位的方法和装置
公开(公告)号：US20100328995A1
公开(公告)日：2010-12-30
申请号：US12715802
申请日：2010-03-02
申请人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

4. 发明授权

US08238149B2 Methods and apparatus for reducing defect bits in phase change memory 有权
标题翻译：用于减少相变存储器中缺陷位的方法和装置
公开(公告)号：US08238149B2
公开(公告)日：2012-08-07
申请号：US12715802
申请日：2010-03-02
申请人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

5. 发明申请

US20110069538A1 MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE 失效
标题翻译：通过改变复位电压，PCM的多级电容编程
公开(公告)号：US20110069538A1
公开(公告)日：2011-03-24
申请号：US12564904
申请日：2009-09-22
申请人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
发明人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.
摘要翻译：相变存储器件及其编程方法。该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。该方法包括确定用于相变存储器件的特征化的RESET电流斜率。该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

6. 发明授权

US07944740B2 Multi-level cell programming of PCM by varying the reset amplitude 失效
标题翻译：通过改变复位幅度对PCM进行多级单元编程
公开(公告)号：US07944740B2
公开(公告)日：2011-05-17
申请号：US12564904
申请日：2009-09-22
申请人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
发明人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.
摘要翻译：相变存储器件及其编程方法。该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。该方法包括确定用于相变存储器件的特征化的RESET电流斜率。该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

7. 发明授权

US08437192B2 3D two bit-per-cell NAND flash memory 有权
标题翻译： 3D双比特单元NAND闪存
公开(公告)号：US08437192B2
公开(公告)日：2013-05-07
申请号：US12785291
申请日：2010-05-21
申请人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
发明人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
IPC分类号： G11C16/00 , G11C16/02 , G11C16/04 , G11C5/02 , G11C5/06
CPC分类号： H01L27/11578 , G11C16/0483 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.
摘要翻译： 3D存储器件包括具有垂直NAND串结构的相应阵列的底部和顶部存储立方体。包括导电材料层的共同源平面位于顶部和底部存储立方体之间。源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

8. 发明授权

US07038928B1 Method of determining optimal voltages for operating two-side non-volatile memory and the operating methods 有权
标题翻译：确定操作双侧非易失性存储器的最佳电压的方法和操作方法
公开(公告)号：US07038928B1
公开(公告)日：2006-05-02
申请号：US10991537
申请日：2004-11-17
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung
IPC分类号： G11C17/00
CPC分类号： G11C16/12 , G11C16/0475 , G11C16/26
摘要： A method of determining an optimal reading voltage for reading a two-side non-volatile memory programmed with a threshold voltage Vt is described. A first side of a memory cell is programmed to Vt, and then an I1-Vg curve of the first side and an I2-Vg curve of the second side are measured, wherein Vg is the gate voltage. A Gm1-Vg curve and a Gm2-Vg curve are plotted, wherein Gm1=dI1/dVg and Gm2=dI2/dVg. The optimal reading voltage VgO is determined as the gate voltage at the intersection of Gm1 and Gm2, corresponding to a maximal total current window Wm (=I2(VgO)−I1(VgO)).
摘要翻译：描述了一种确定用于读取用阈值电压Vt编程的双侧非易失性存储器的最佳读取电压的方法。存储器单元的第一侧被编程为Vt，然后第二侧的I 1 -T 1 -V G曲线和第二侧的I 2 -V -V曲线是测量，其中Vg是栅极电压。绘制了一个Gm 1-ΔVg曲线和一个Gm 2 -V -G曲线，其中G m 1 = 1/1 / / dVg和Gm2 = dI2 / dVg。确定最佳读取电压V g O O N作为在最大总电流窗口Gm1和Gm2的交点处的栅极电压 Wm（= I 2）（V g O O） - I 1（V g O O））。

9. 发明授权

US08324605B2 Dielectric mesh isolated phase change structure for phase change memory 有权
标题翻译：介质网隔离相变结构相变记忆
公开(公告)号：US08324605B2
公开(公告)日：2012-12-04
申请号：US12286874
申请日：2008-10-02
申请人： Hsiang-Lan Lung , Chieh-Fang Chen , Yen-Hao Shih , Ming-Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
发明人： Hsiang-Lan Lung , Chieh-Fang Chen , Yen-Hao Shih , Ming-Hsiu Lee , Matthew J. Breitwisch , Chung Hon Lam , Frieder H. Baumann , Philip Flaitz , Simone Raoux
IPC分类号： H01L47/00 , H01L21/06
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.
摘要翻译：使用氧化硅掺杂的硫族化物材料来描述用于制造存储器件的方法和所得到的器件。具有接触表面的第一电极; 形成包括与第一电极的接触表面接触的部分的多晶状态的相变记忆材料体以及与相变材料体接触的第二电极。该方法包括在相变材料体内的有源区内熔化和冷却相变存储材料一次或多次，而不会干扰有源区外的多晶态。导致活性区域中的氧化硅网格与至少一个硫族化物材料结构域形成。此外，活性区域外的多晶态的相变材料的晶粒尺寸小，结果更均匀。

10. 发明申请

US20100328996A1 PHASE CHANGE MEMORY HAVING ONE OR MORE NON-CONSTANT DOPING PROFILES 有权
标题翻译：具有一个或多个不间断的配置文件的相位更改记忆
公开(公告)号：US20100328996A1
公开(公告)日：2010-12-30
申请号：US12729837
申请日：2010-03-23
申请人： YEN-HAO SHIH , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming-Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung Hon Lam
发明人： YEN-HAO SHIH , Huai-Yu Cheng , Chieh-Fang Chen , Chao-I Wu , Ming-Hsiu Lee , Hsiang-Lan Lung , Matthew J. Breitwisch , Simone Raoux , Chung Hon Lam
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L45/1625 , G11C13/0004 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/1641
摘要： A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.
摘要翻译：一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布。根据不同的晶体学，热学和电学条件以及不同的相变条件，使用“非恒定”浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

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