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1. 发明授权

US08238149B2 Methods and apparatus for reducing defect bits in phase change memory 有权
标题翻译：用于减少相变存储器中缺陷位的方法和装置
公开(公告)号：US08238149B2
公开(公告)日：2012-08-07
申请号：US12715802
申请日：2010-03-02
申请人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： Yen-Hao Shih , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

2. 发明申请

US20100328995A1 METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY 有权
标题翻译：减少相变记忆中缺陷位的方法和装置
公开(公告)号：US20100328995A1
公开(公告)日：2010-12-30
申请号：US12715802
申请日：2010-03-02
申请人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
发明人： YEN-HAO SHIH , Ming-Hsiu Lee , Chao-I Wu , Hsiang-Lan Lung , Chung Hon Lam , Roger Cheek , Matthew J. Breitwisch , Bipin Rajendran
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/004 , G11C29/70 , G11C2213/79
摘要： Phase change memory devices and methods for operating described herein are based on the discovery that, following an initial high current operation applied to a phase change memory cell to establish the high resistance reset state, the current-voltage (I-V) behavior of the memory cell under different bias voltages can be used to detect if the memory cell is a defect cell having poor data retention characteristics.
摘要翻译：相位变化存储器件和这里描述的操作方法基于以下发现：在施加到相变存储器单元以建立高电阻复位状态的初始高电流操作之后，存储器单元的电流 - 电压（IV）行为可以使用不同的偏置电压来检测存储器单元是否具有差的数据保留特性的缺陷单元。

3. 发明授权

US08350316B2 Phase change memory cells having vertical channel access transistor and memory plane 有权
标题翻译：具有垂直通道存取晶体管和存储器平面的相变存储单元
公开(公告)号：US08350316B2
公开(公告)日：2013-01-08
申请号：US12471287
申请日：2009-05-22
申请人： Hsiang-Lan Lung , Chung Hon Lam , Ming-Hsiu Lee , Bipin Rajendran
发明人： Hsiang-Lan Lung , Chung Hon Lam , Ming-Hsiu Lee , Bipin Rajendran
IPC分类号： H01L29/732
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的相应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻多行字线中的字线。相应的字线用作场效应晶体管的栅极。电介质将对应的字线与沟道区分开。存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

4. 发明授权

US08030635B2 Polysilicon plug bipolar transistor for phase change memory 有权
标题翻译：用于相变存储器的多晶硅插头双极晶体管
公开(公告)号：US08030635B2
公开(公告)日：2011-10-04
申请号：US12353219
申请日：2009-01-13
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung Hon Lam
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung Hon Lam
IPC分类号： H01L29/02
CPC分类号： H01L45/04 , G11C13/0004 , H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.
摘要翻译：本文描述了存储器件和制造方法。本文描述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极与多个字线中的对应字线接触以限定pn结。双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。

5. 发明申请

US20090185411A1 INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS 审中-公开
标题翻译：集成电路，包括二极管记忆体
公开(公告)号：US20090185411A1
公开(公告)日：2009-07-23
申请号：US12017581
申请日：2008-01-22
申请人： Thomas Happ , Chung Hon Lam , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
发明人： Thomas Happ , Chung Hon Lam , Hsiang-Lan Lung , Bipin Rajendran , Min Yang
IPC分类号： G11C11/00 , H01L21/06
CPC分类号： H01L27/24 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2213/71 , G11C2213/72
摘要： The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.
摘要翻译：集成电路包括耦合到第一金属线的第一金属线和第一二极管。集成电路包括耦合到第一二极管的第一电阻率变化材料和耦合到第一电阻率变化材料的第二金属线。

6. 发明申请

US20090268507A1 PHASE CHANGE MEMORY DEVICE AND METHOD OF MANUFACTURE 失效
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090268507A1
公开(公告)日：2009-10-29
申请号：US12111258
申请日：2008-04-29
申请人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： G11C11/00 , H01S4/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/1253 , Y10T29/49002
摘要： A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase change memory element, and an electrically conductive bottom layer coupled to the outer ring electrode.
摘要翻译：公开了一种相变存储器控制环下电极。下电极包括与相变存储元件热接触的外环电极，设置在外环电极内并与相变存储元件接触的内种子层，以及耦合到外环电极的导电底层。

7. 发明授权

US07868313B2 Phase change memory device and method of manufacture 失效
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07868313B2
公开(公告)日：2011-01-11
申请号：US12111258
申请日：2008-04-29
申请人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Chung H. Lam , Hsiang-Lan Lung , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L45/06 , H01L45/1233 , H01L45/1253 , Y10T29/49002
摘要： A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase change memory element, and an electrically conductive bottom layer coupled to the outer ring electrode.
摘要翻译：公开了一种相变存储器控制环下电极。下电极包括与相变存储元件热接触的外环电极，设置在外环电极内并与相变存储元件接触的内种子层，以及耦合到外环电极的导电底层。

8. 发明申请

US20100295009A1 Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane 有权
标题翻译：具有垂直通道访问晶体管和存储器平面的相变存储单元
公开(公告)号：US20100295009A1
公开(公告)日：2010-11-25
申请号：US12471287
申请日：2009-05-22
申请人： Hsiang-Lan Lung , Chung H. Lam , Ming-Hsiu Lee , Bipin Rajendran
发明人： Hsiang-Lan Lung , Chung H. Lam , Ming-Hsiu Lee , Bipin Rajendran
IPC分类号： H01L47/00 , H01L21/00
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的对应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻多行字线中的字线。相应的字线用作场效应晶体管的栅极。电介质将对应的字线与沟道区分开。存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

9. 发明授权

US08589320B2 Area efficient neuromorphic system that connects a FET in a diode configuration, and a variable resistance material to junctions of neuron circuit blocks 有权
标题翻译：将二极管配置中的FET和可变电阻材料连接到神经元电路块的结的区域有效的神经元系统
公开(公告)号：US08589320B2
公开(公告)日：2013-11-19
申请号：US13548532
申请日：2012-07-13
申请人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
IPC分类号： G06E1/00
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic system includes a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks. The plurality of synapse blocks includes a plurality of neuromorphic circuits. Each neuromorphic circuit includes a field effect transistor in a diode configuration electrically connected to variable resistance material, where the variable resistance material provides a programmable resistance value. Each neuromorphic circuit also includes a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks, and a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks.
摘要翻译：神经元系统包括电连接到多个神经元电路块的多个突触块。多个突触块包括多个神经形态电路。每个神经形态电路包括电连接到可变电阻材料的二极管配置中的场效应晶体管，其中可变电阻材料提供可编程电阻值。每个神经形态电路还包括电连接到可变电阻材料的第一结和一个或多个神经元电路块的输出，以及电连接到场效应晶体管的第二结和一个或多个神经元电路的输入块。

10. 发明授权

US08311965B2 Area efficient neuromorphic circuits using field effect transistors (FET) and variable resistance material 有权
标题翻译：使用场效应晶体管（FET）和可变电阻材料的区域效率的神经元电路
公开(公告)号：US08311965B2
公开(公告)日：2012-11-13
申请号：US12620624
申请日：2009-11-18
申请人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
IPC分类号： G06F17/00
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic circuit includes a first field effect transistor in a first diode configuration establishing an electrical connection between a first gate and a first drain of the first field effect transistor. The neuromorphic circuit also includes a second field effect transistor in a second diode configuration establishing an electrical connection between a second gate and a second drain of the second field effect transistor. The neuromorphic circuit further includes variable resistance material electrically connected to both the first drain and the second drain, where the variable resistance material provides a programmable resistance value. The neuromorphic circuit additionally includes a first junction electrically connected to the variable resistance material and providing a first connection point to an output of a neuron circuit, and a second junction electrically connected to the variable resistance material and providing a second connection point to the output of the neuron circuit.
摘要翻译：神经形态电路包括在第一二极管配置中建立第一场效应晶体管的第一栅极和第一漏极之间的电连接的第一场效应晶体管。神经形态电路还包括在第二二极管配置中建立第二场效应晶体管的第二栅极和第二漏极之间的电连接的第二场效应晶体管。神经形态电路还包括电连接到第一漏极和第二漏极的可变电阻材料，其中可变电阻材料提供可编程电阻值。神经形态电路还包括电连接到可变电阻材料并且提供到神经元电路的输出的第一连接点的第一结，以及电连接到可变电阻材料并且提供第二连接点到第二连接点的第二连接点神经元电路。

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