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1. 发明授权

US09666671B2 Semiconductor device with composite drift region and related fabrication method 有权
公开(公告)号：US09666671B2
公开(公告)日：2017-05-30
申请号：US14279991
申请日：2014-05-16
申请人： Zhihong Zhang , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/10 , H01L29/78 , H01L29/66 , H01L29/36 , H01L29/06 , H01L29/08 , H01L21/265
CPC分类号： H01L29/1045 , H01L21/26513 , H01L21/2652 , H01L29/0653 , H01L29/0847 , H01L29/36 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section.

2. 发明授权

US09385229B2 Semiconductor device with improved breakdown voltage 有权
标题翻译：具有提高击穿电压的半导体器件
公开(公告)号：US09385229B2
公开(公告)日：2016-07-05
申请号：US14495508
申请日：2014-09-24
申请人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7824 , H01L29/0623 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/7835 , H01L29/78624
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material.
摘要翻译：提供半导体器件结构和相关的制造方法。示例性的半导体器件结构包括具有第一导电类型和第一掺杂剂浓度的第一半导体材料区域，具有覆盖第一区域的第二导电类型的第二半导体材料区域，具有第一导电类型的半导体材料的漂移区域覆盖第二区域，以及具有第一导电类型的半导体材料的漏极区域。漂移区域和漏极区域电连接，漂移区域的至少一部分位于漏极区域和第二区域之间，并且第二区域的至少一部分位于该漂移区域和第一区域之间。在一个或多个示例性实施例中，第一区域邻接介电材料的下层绝缘层。

3. 发明授权

US09165918B1 Composite semiconductor device with multiple threshold voltages 有权
标题翻译：具有多个阈值电压的复合半导体器件
公开(公告)号：US09165918B1
公开(公告)日：2015-10-20
申请号：US14272027
申请日：2014-05-07
申请人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L27/02 , H01L29/78 , H01L29/08 , H01L29/10 , H01L27/088 , H01L21/8234 , H01L21/265
CPC分类号： H01L27/0248 , H01L21/26513 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L27/0266 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1045 , H01L29/1079 , H01L29/1095 , H01L29/66575 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor.
摘要翻译：一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构，另一个。第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。第一多个晶体管结构的每个晶体管结构包括非均匀沟道，使得第一构成晶体管具有比第二构成晶体管更高的阈值电压电平。

4. 发明授权

US09136323B2 Drain-end drift diminution in semiconductor devices 有权
标题翻译：半导体器件的漏极漂移减少
公开(公告)号：US09136323B2
公开(公告)日：2015-09-15
申请号：US14486104
申请日：2014-09-15
申请人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L29/063 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.
摘要翻译：制造晶体管的方法包括在衬底中形成场隔离区域。在形成场隔离区之后，将掺杂剂注入到用于形成漂移区的衬底的第一区域中。漏极区形成在衬底的第二区域中。第一和第二区域横向重叠以限定晶体管的导电路径。第一区域不横向跨越第二区域延伸。

5. 发明申请

US20150056751A1 DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS 有权
标题翻译： DIE边缘密封结构和相关制造方法
公开(公告)号：US20150056751A1
公开(公告)日：2015-02-26
申请号：US14505842
申请日：2014-10-03
申请人： Zhihong Zhang , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L23/00 , H01L21/78
CPC分类号： H01L23/562 , H01L21/78 , H01L23/3171 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.
摘要翻译：提供电子器件的模具结构和相关的制造方法。示例性的管芯结构包括半导体衬底的切割部分，其包括其上制造有一个或多个半导体器件的器件区域和在该半导体衬底内限定器件区域的边缘密封结构。在一个或多个实施例中，边缘密封结构包括接触半导体材料的手柄层的导电材料，形成在密封结构上方的裂缝结构，其中裂缝结构和边缘密封结构在手柄层之间提供电连接以及覆盖在手柄层上的介电材料的掩埋层的半导体材料的有源层。

6. 发明申请

US20150004768A1 DRAIN-END DRIFT DIMINUTION IN SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件中的引出端DRIFT分解
公开(公告)号：US20150004768A1
公开(公告)日：2015-01-01
申请号：US14486104
申请日：2014-09-15
申请人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/06 , H01L29/66 , H01L29/10
CPC分类号： H01L29/063 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.
摘要翻译：制造晶体管的方法包括在衬底中形成场隔离区域。在形成场隔离区之后，将掺杂剂注入到用于形成漂移区的衬底的第一区域中。漏极区形成在衬底的第二区域中。第一和第二区域横向重叠以限定晶体管的导电路径。第一区域不横向跨越第二区域延伸。

7. 发明授权

US09640635B2 Reliability in mergeable semiconductor devices 有权
公开(公告)号：US09640635B2
公开(公告)日：2017-05-02
申请号：US14832139
申请日：2015-08-21
申请人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L27/01 , H01L21/336 , H01L29/66 , H01L29/786 , H01L21/265 , H01L29/06 , H01L29/08 , H01L29/10 , H01L21/8234 , H01L29/36 , H01L27/088 , H01L21/761 , H01L21/762
CPC分类号： H01L29/66659 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L27/088 , H01L29/0642 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/36 , H01L29/66575 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/786 , H01L29/78615 , H01L29/78624 , H01L29/78654
摘要： A method of fabricating a transistor device having a channel of a first conductivity type formed during operation in a body region having a second conductivity type includes forming a first well region of the body region in a semiconductor substrate, performing a first implantation procedure to counter-dope the first well region with dopant of the first conductivity type to define a second well region of the body region, and performing a second implantation procedure to form a source region in the first well region and a drain region in the second well region.

8. 发明授权

US09490322B2 Semiconductor device with enhanced 3D resurf 有权
标题翻译：具有增强3D复现功能的半导体器件
公开(公告)号：US09490322B2
公开(公告)日：2016-11-08
申请号：US13748076
申请日：2013-01-23
申请人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/94 , H01L29/08 , H01L29/78 , H01L29/06 , H01L29/10
CPC分类号： H01L29/66681 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/7835
摘要： A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的源极和漏极区域以及沿着第一横向尺寸彼此间隔开的半导体衬底中的漂移区域，并且在施加偏置电压之前电荷载体在操作期间漂移源极和漏极区域。漂移区域沿着漂移区域和漏极区域之间的界面在第二横向维度上具有缺口掺杂剂分布。

9. 发明申请

US20150325565A1 Composite Semiconductor Device with Multiple Threshold Voltages 有权
标题翻译：具有多个阈值电压的复合半导体器件
公开(公告)号：US20150325565A1
公开(公告)日：2015-11-12
申请号：US14272027
申请日：2014-05-07
申请人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L27/02 , H01L29/08 , H01L21/265 , H01L29/66 , H01L27/088 , H01L21/8234 , H01L29/78 , H01L29/10
CPC分类号： H01L27/0248 , H01L21/26513 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L27/0266 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1045 , H01L29/1079 , H01L29/1095 , H01L29/66575 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor.
摘要翻译：一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构，另一个。第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。第一多个晶体管结构的每个晶体管结构包括非均匀沟道，使得第一构成晶体管具有比第二构成晶体管更高的阈值电压电平。

10. 发明授权

US09117841B2 Mergeable semiconductor device with improved reliability 有权
标题翻译：合并半导体器件具有可靠性提高
公开(公告)号：US09117841B2
公开(公告)日：2015-08-25
申请号：US14047348
申请日：2013-10-07
申请人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L27/01 , H01L21/336 , H01L29/66 , H01L29/786
CPC分类号： H01L29/66659 , H01L21/26513 , H01L21/761 , H01L21/76224 , H01L21/823418 , H01L21/823481 , H01L27/088 , H01L29/0642 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/1095 , H01L29/36 , H01L29/66575 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/786 , H01L29/78615 , H01L29/78624 , H01L29/78654
摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate, having a first conductivity type, and laterally spaced from one another, and a composite body region disposed in the semiconductor substrate and having a second conductivity type. The composite body region includes a first well region that extends laterally across the source and drain regions and a second well region disposed in the first well region. The drain region is disposed in the second well region such that charge carriers flow from the first well region into the second well region to reach the drain region. The second well region includes dopant of the first conductivity type to have a lower net dopant concentration level than the first well region. A pocket may be disposed in a drain extension region and configured to establish a depletion region along an edge of a gate structure.
摘要翻译：一种器件包括半导体衬底，设置在半导体衬底中的源极和漏极区域，具有第一导电类型，并且彼此横向间隔开;以及复合体区域，设置在半导体衬底中并且具有第二导电类型。复合体区域包括沿着源极和漏极区域横向延伸的第一阱区域和设置在第一阱区域中的第二阱区域。漏极区域设置在第二阱区域中，使得载流子从第一阱区域流入第二阱区域以到达漏极区域。第二阱区域包括具有比第一阱区域更低的净掺杂剂浓度水平的第一导电类型的掺杂剂。凹槽可以设置在漏极延伸区域中并且被配置成沿着栅极结构的边缘建立耗尽区域。

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