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    • 1. 发明申请
    • THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME
    • 薄膜晶体管阵列基板及其制造方法
    • US20080042133A1
    • 2008-02-21
    • US11756855
    • 2007-06-01
    • Hong-Kee CHINSang-Gab KIMMin-Seok OHJoo-Han KIM
    • Hong-Kee CHINSang-Gab KIMMin-Seok OHJoo-Han KIM
    • H01L29/12H01L21/336
    • H01L27/1288H01L27/12H01L27/1248
    • A thin film transistor (TFT) array substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion, and a method of fabricating the TFT array substrate. The TFT array substrate includes a gate interconnection line arranged on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode, and a drain electrode arranged on the semiconductor layer, a first passivation film arranged on the data interconnection line and exposing the drain electrode, a second passivation film arranged on the first passivation film, and a pixel electrode electrically connected with the drain electrode. An outer sidewall of the second passivation film is positioned inside an outer sidewall of the first passivation film.
    • 提供一种薄膜晶体管(TFT)阵列基板,其中在接触部分中提供导电材料之间的足够大的接触面积,以及制造TFT阵列基板的方法。 TFT阵列基板包括布置在绝缘基板上的栅极互连线,覆盖栅极互连线的栅极绝缘层,布置在栅极绝缘层上的半导体层,包括数据线,源极和 布置在半导体层上的漏电极,布置在数据互连线上并暴露漏极的第一钝化膜,布置在第一钝化膜上的第二钝化膜和与漏电极电连接的像素电极。 第二钝化膜的外侧壁位于第一钝化膜的外侧壁内。
    • 7. 发明申请
    • THIN FILM TRANSISTOR PANEL AND MANUFACTURING METHOD OF THE SAME
    • 薄膜晶体管面板及其制造方法
    • US20090224257A1
    • 2009-09-10
    • US12390076
    • 2009-02-20
    • Hong-Kee CHINShin-Il CHOISang-Gab KIMMin-Seok OHYu-Gwang JEONGSeung-Ha CHOIDong-Ju YANG
    • Hong-Kee CHINShin-Il CHOISang-Gab KIMMin-Seok OHYu-Gwang JEONGSeung-Ha CHOIDong-Ju YANG
    • H01L33/00
    • H01L29/458H01L27/124
    • A thin film transistor array panel includes a gate line formed on a substrate and including a gate electrode, a semiconductor layer formed on a surface of the substrate having the gate line, a data line formed on the semiconductor layer, insulatedly intersecting the gate line, and including a source electrode disposed on the gate electrode, a drain electrode separated from the source electrode by a channel, disposed on the gate electrode, and formed from the same layer as the data line, a passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode, and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole. The data line and the drain electrode may include a first layer and a second layer formed on the first layer, a planar edge of the first layer protrudes from a planar edge of the second layer, and the first layer is formed by dry-etching and the second layer is formed by wet-etching.
    • 薄膜晶体管阵列面板包括形成在基板上并包括栅电极的栅极线,形成在具有栅极线的基板的表面上的半导体层,形成在半导体层上的与栅极线绝缘相交的数据线, 并且包括设置在栅电极上的源电极,通过沟道与源电极分离的漏极,设置在栅电极上,并由与数据线相同的层形成,形成在数据线上的钝化层和 漏极,并且具有暴露漏电极的第一接触孔,以及形成在钝化层上并通过第一接触孔接触漏电极的像素电极。 数据线和漏极可以包括形成在第一层上的第一层和第二层,第一层的平面边缘从第二层的平坦边缘突出,并且第一层通过干蚀刻形成, 第二层通过湿法蚀刻形成。