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1. 发明申请

US20090224257A1 THIN FILM TRANSISTOR PANEL AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：薄膜晶体管面板及其制造方法
公开(公告)号：US20090224257A1
公开(公告)日：2009-09-10
申请号：US12390076
申请日：2009-02-20
申请人： Hong-Kee CHIN , Shin-Il CHOI , Sang-Gab KIM , Min-Seok OH , Yu-Gwang JEONG , Seung-Ha CHOI , Dong-Ju YANG
发明人： Hong-Kee CHIN , Shin-Il CHOI , Sang-Gab KIM , Min-Seok OH , Yu-Gwang JEONG , Seung-Ha CHOI , Dong-Ju YANG
IPC分类号： H01L33/00
CPC分类号： H01L29/458 , H01L27/124
摘要： A thin film transistor array panel includes a gate line formed on a substrate and including a gate electrode, a semiconductor layer formed on a surface of the substrate having the gate line, a data line formed on the semiconductor layer, insulatedly intersecting the gate line, and including a source electrode disposed on the gate electrode, a drain electrode separated from the source electrode by a channel, disposed on the gate electrode, and formed from the same layer as the data line, a passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode, and a pixel electrode formed on the passivation layer and contacting the drain electrode through the first contact hole. The data line and the drain electrode may include a first layer and a second layer formed on the first layer, a planar edge of the first layer protrudes from a planar edge of the second layer, and the first layer is formed by dry-etching and the second layer is formed by wet-etching.
摘要翻译：薄膜晶体管阵列面板包括形成在基板上并包括栅电极的栅极线，形成在具有栅极线的基板的表面上的半导体层，形成在半导体层上的与栅极线绝缘相交的数据线，并且包括设置在栅电极上的源电极，通过沟道与源电极分离的漏极，设置在栅电极上，并由与数据线相同的层形成，形成在数据线上的钝化层和漏极，并且具有暴露漏电极的第一接触孔，以及形成在钝化层上并通过第一接触孔接触漏电极的像素电极。数据线和漏极可以包括形成在第一层上的第一层和第二层，第一层的平面边缘从第二层的平坦边缘突出，并且第一层通过干蚀刻形成，第二层通过湿法蚀刻形成。

2. 发明申请

US20110097961A1 DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示面板及其制造方法
公开(公告)号：US20110097961A1
公开(公告)日：2011-04-28
申请号：US12981287
申请日：2010-12-29
申请人： Min-Seok OH , Yang-Ho BAE , Pil-Sang YUN , Byeong-Beom KIM , Seung-Ha CHOI , Sang-Gab KIM , Chang-Ho JEONG , Shin-Il CHOI , Hong-Kee CHIN , Yu-Gwang JEONG , Dong-Ju YANG
发明人： Min-Seok OH , Yang-Ho BAE , Pil-Sang YUN , Byeong-Beom KIM , Seung-Ha CHOI , Sang-Gab KIM , Chang-Ho JEONG , Shin-Il CHOI , Hong-Kee CHIN , Yu-Gwang JEONG , Dong-Ju YANG
IPC分类号： H01J9/20
CPC分类号： H01L27/12 , G02F2001/136295 , H01L27/124 , H01L29/458
摘要： In a display panel and a method of manufacturing the display panel, a gate line, a data line, and source and drain electrodes including a same material as the data line are formed on a substrate constituting the display panel, and the data line includes an aluminum based alloy containing sufficient nickel to inhibit corrosion during dry etching. The corrosion resistance of the AlNi-containing alloy helps prevent corrosion of the data line, the source electrode, and the drain electrode during selective dry etching that shapes these lines and electrodes.
摘要翻译：在显示面板和制造显示面板的方法中，在构成显示面板的基板上形成包括与数据线相同材料的栅极线，数据线以及源极和漏极，并且数据线包括铝基合金含有足够的镍以在干蚀刻期间抑制腐蚀。含有AlNi的合金的耐腐蚀性有助于防止在形成这些线和电极的选择性干蚀刻期间数据线，源电极和漏电极的腐蚀。

3. 发明申请

US20110024752A1 THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME 有权
标题翻译：薄膜晶体管，其制造方法和显示装置
公开(公告)号：US20110024752A1
公开(公告)日：2011-02-03
申请号：US12900634
申请日：2010-10-08
申请人： Shin-Il CHOI , Sang-Gab KIM , Hong-Kee CHIN , Min-Seok OH , Yu-Gwang JEONG , Seung-Ha CHOI
发明人： Shin-Il CHOI , Sang-Gab KIM , Hong-Kee CHIN , Min-Seok OH , Yu-Gwang JEONG , Seung-Ha CHOI
IPC分类号： H01L29/16 , H01L33/16
CPC分类号： H01L27/124 , H01L29/458 , H01L29/66765
摘要： A method of fabricating a thin film transistor includes forming a gate electrode on a substrate, forming a semiconductor layer on the gate electrode, forming a source electrode on the semiconductor layer, forming a drain electrode on the semiconductor layer spaced apart from the source electrode, forming a copper layer pattern on the source electrode and the drain electrode, exposing the copper layer pattern on the source electrode and the drain electrode to a fluorine-containing process gas to form a copper fluoride layer pattern thereon, and patterning the semiconductor layer.
摘要翻译：一种薄膜晶体管的制造方法，包括在基板上形成栅电极，在栅电极上形成半导体层，在半导体层上形成源电极，在与源电极间隔开的半导体层上形成漏电极，在源电极和漏电极上形成铜层图案，将源电极和漏电极上的铜层图案暴露于含氟处理气体，以在其上形成氟化铜层图案，并对该半导体层进行构图。

4. 发明申请

US20100044717A1 THIN FILM TRANSISTOR PANEL AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管板及其制造方法
公开(公告)号：US20100044717A1
公开(公告)日：2010-02-25
申请号：US12434942
申请日：2009-05-04
申请人： Seung-Ha CHOI , Ki-Yeup LEE , Sang-Gab KIM , Shin-Il CHOI , Dong-Ju YANG , Hong-Kee CHIN , Yu-Gwang JEONG , Ji-Young PARK , Dong-Hoon LEE , Byeong-Beom KIM
发明人： Seung-Ha CHOI , Ki-Yeup LEE , Sang-Gab KIM , Shin-Il CHOI , Dong-Ju YANG , Hong-Kee CHIN , Yu-Gwang JEONG , Ji-Young PARK , Dong-Hoon LEE , Byeong-Beom KIM
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/458 , H01L27/124 , H01L29/4908
摘要： After forming a signal line including aluminum, an upper layer of an oxide layer including aluminum that covers the signal line is formed in the same chamber and by using the same sputtering target as the signal line, or a buffer layer of an oxide layer including aluminum is formed in a contact hole exposing the signal line during the formation of the contact hole. Accordingly, the contact characteristic between an upper layer including indium tin oxide (“ITO”) or indium zinc oxide (“IZO”) and the signal line may be improved to enhance the adhesion therebetween while not increasing the production cost of the thin film transistor (“TFT”) array panel.
摘要翻译：在形成包括铝的信号线之后，在相同的室中形成包含覆盖信号线的铝的氧化物层的上层，并且通过使用与信号线相同的溅射靶，或者包括铝的氧化物层的缓冲层形成在接触孔形成期间暴露信号线的接触孔中。因此，可以改善包括氧化铟锡（“ITO”）或氧化铟锌（“IZO”）的上层与信号线之间的接触特性，以增强其之间的粘附，同时不增加薄膜晶体管的生产成本（“TFT”）阵列面板。

5. 发明申请

US20100136775A1 METHOD OF MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE 审中-公开
标题翻译：制造薄膜晶体管基板的方法
公开(公告)号：US20100136775A1
公开(公告)日：2010-06-03
申请号：US12607567
申请日：2009-10-28
申请人： Seung-Ha CHOI , Sang-Gab KIM , Bong-Kyu SHIN , Sang-Uk LIM , Jin-Ho JU , Sung-Hoon YANG , Sang-Woo WHANGBO , Jae-Ho CHOI , Ki-Yeup LEE , Yun-Jong YEO , Shin-Il CHOI , Dong-Ju YANG , Hong-Kee CHIN , Yu-Gwang JEONG
发明人： Seung-Ha CHOI , Sang-Gab KIM , Bong-Kyu SHIN , Sang-Uk LIM , Jin-Ho JU , Sung-Hoon YANG , Sang-Woo WHANGBO , Jae-Ho CHOI , Ki-Yeup LEE , Yun-Jong YEO , Shin-Il CHOI , Dong-Ju YANG , Hong-Kee CHIN , Yu-Gwang JEONG
IPC分类号： H01L21/28
CPC分类号： H01L29/4908 , H01L27/1225 , H01L27/1248 , H01L29/458 , H01L29/7869
摘要： Provided is a method for manufacturing a thin-film transistor substrate, in which the etching characteristics of an insulating film and a passivation layer are enhanced. The insulating film and the passivation layer are deposited by low temperature chemical vapor deposition. The method includes disposing a gate wiring on an insulating substrate; disposing a gate insulating film on the gate wiring; disposing a data wiring on the gate insulating film; disposing a passivation layer on the data wiring; and forming a contact hole by etching at least one of the gate insulating film and the passivation layer, wherein at least one of the gate insulating film and the passivation layer is disposed at a temperature of about 280° C. or below, and the forming of the contact hole is performed at a pressure of about 60 mT or below.
摘要翻译：提供一种制造薄膜晶体管基板的方法，其中提高了绝缘膜和钝化层的蚀刻特性。通过低温化学气相沉积沉积绝缘膜和钝化层。该方法包括在绝缘基板上设置栅极布线; 在栅极布线上设置栅极绝缘膜; 在栅极绝缘膜上设置数据布线; 在数据线上设置钝化层; 以及通过蚀刻所述栅极绝缘膜和所述钝化层中的至少一个来形成接触孔，其中所述栅极绝缘膜和所述钝化层中的至少一个设置在约280℃或更低的温度下，并且所述形成的接触孔在约60mT以下的压力下进行。

6. 发明申请

US20110297931A1 METHOD OF FABRICATING A THIN FILM TRANSISTOR ARRAY SUBSTRATE 有权
标题翻译：薄膜晶体管阵列基板的制作方法
公开(公告)号：US20110297931A1
公开(公告)日：2011-12-08
申请号：US13210282
申请日：2011-08-15
申请人： Dong-Ju YANG , Yu-Gwang JEONG , Ki-Yeup LEE , Sang-Gab KIM , Yun-Jong YEO , Shin-Il CHOI , Hong-Kee CHIN , Seung-Ha CHOI , Jung-Suk BANG
发明人： Dong-Ju YANG , Yu-Gwang JEONG , Ki-Yeup LEE , Sang-Gab KIM , Yun-Jong YEO , Shin-Il CHOI , Hong-Kee CHIN , Seung-Ha CHOI , Jung-Suk BANG
IPC分类号： H01L29/786
CPC分类号： H01L27/1248 , H01L27/1214 , H01L27/1225 , H01L27/1288 , H01L29/7869
摘要： A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.
摘要翻译：提出了制造薄膜晶体管阵列基板的方法。该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到作为数据互连线的延伸线的漏电极。在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。形成连接到漏电极的像素电极。两个钝化层具有相同的组成，但是在不同的温度下进行处理。还提出了以上述方式制备的薄膜晶体管。

7. 发明申请

US20090278126A1 METAL LINE SUBSTRATE, THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：金属线基板，薄膜晶体管基板及其形成方法
公开(公告)号：US20090278126A1
公开(公告)日：2009-11-12
申请号：US12431969
申请日：2009-04-29
申请人： Dong-Ju YANG , Sang-Gab KIM , Ki-Yeup LEE , Yun-Jong YEO , Shin-Il CHOI , Hong-Kee CHIN , Yu-Gwang JEONG , Seung-Ha CHOI
发明人： Dong-Ju YANG , Sang-Gab KIM , Ki-Yeup LEE , Yun-Jong YEO , Shin-Il CHOI , Hong-Kee CHIN , Yu-Gwang JEONG , Seung-Ha CHOI
IPC分类号： H01L29/786 , H01L23/522 , H01L21/768
CPC分类号： H01L21/76879 , H01L27/124
摘要： A metal line substrate and a method of fabricating thereof, the metal line substrate including an insulating layer and a capping layer disposed on an insulating substrate, a trench defined by the insulating layer and the capping layer disposed on the insulating substrate, a seed layer pattern disposed on the insulating substrate, and a low-resistive conductive layer pattern disposed in the trench and contacting the seed layer pattern. The capping layer pattern includes a protrusion region which is in contact with the low-resistive conductive layer pattern.
摘要翻译：一种金属线基板及其制造方法，所述金属线基板包括绝缘层和设置在绝缘基板上的覆盖层，由绝缘层限定的沟槽和设置在绝缘基板上的覆盖层，种子层图案设置在绝缘基板上，以及设置在沟槽中并接触种子层图案的低电阻导电层图案。覆盖层图案包括与低电阻导电层图案接触的突起区域。

8. 发明申请

US20120003768A1 THIN FLIM TRANSISTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄片晶体管基板及其制造方法
公开(公告)号：US20120003768A1
公开(公告)日：2012-01-05
申请号：US13231225
申请日：2011-09-13
申请人： Hong-Kee CHIN , Sang-Gab KIM , Woong-Kwon KIM , Yong-Mo CHOI , Seung-Ha CHOI , Shin-Il CHOI , Ho-Jun LEE , Jung-Suk BANG , Yu-Gwang JEONG
发明人： Hong-Kee CHIN , Sang-Gab KIM , Woong-Kwon KIM , Yong-Mo CHOI , Seung-Ha CHOI , Shin-Il CHOI , Ho-Jun LEE , Jung-Suk BANG , Yu-Gwang JEONG
IPC分类号： H01L33/16
CPC分类号： H01L27/12 , H01L27/1248 , H01L27/1288
摘要： A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.
摘要翻译：提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。

9. 发明申请

US20100148182A1 THIN FLIM TRANSISTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：薄片晶体管基板及其制造方法
公开(公告)号：US20100148182A1
公开(公告)日：2010-06-17
申请号：US12429388
申请日：2009-04-24
申请人： Hong-Kee CHIN , Sang-Gab KIM , Woong-Kwon KIM , Yong-Mo CHOI , Seung-Ha CHOI , Shin-Il CHOI , Ho-Jun LEE , Jung-Suk BANG , Yu-Gwang JEONG
发明人： Hong-Kee CHIN , Sang-Gab KIM , Woong-Kwon KIM , Yong-Mo CHOI , Seung-Ha CHOI , Shin-Il CHOI , Ho-Jun LEE , Jung-Suk BANG , Yu-Gwang JEONG
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/12 , H01L27/1248 , H01L27/1288
摘要： A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.
摘要翻译：提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。

10. 发明申请

US20130015452A1 ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE 审中-公开
标题翻译：阵列基板和制造阵列基板的方法
公开(公告)号：US20130015452A1
公开(公告)日：2013-01-17
申请号：US13616150
申请日：2012-09-14
申请人： Shin-Il CHOI , Sang-Gab KIM , Yu-Gwang JEONG , Hong-Kee CHIN
发明人： Shin-Il CHOI , Sang-Gab KIM , Yu-Gwang JEONG , Hong-Kee CHIN
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/1288 , H01L29/42384 , H01L29/78696
摘要： An array substrate including: a gate electrode and a gate insulation layer disposed on a base substrate, the gate insulation layer having a first thickness in a first region and a second thickness in a second region, the first thickness being greater than the second thickness; a semiconductor pattern disposed on the gate insulation layer in the first region, an end portion of the semiconductor pattern having a stepped portion with respect to the gate insulation layer; an ohmic contact pattern disposed on the semiconductor pattern, an end portion of the ohmic contact pattern opposite to a channel portion being aligned with the end portion of the semiconductor pattern; and source and drain electrodes disposed on the ohmic contact pattern, the source and drain electrodes spaced apart from each other and including first and second thin-film transistor patterns.
摘要翻译：一种阵列基板，包括：栅极电极和栅极绝缘层，其设置在基底基板上，所述栅极绝缘层在第一区域具有第一厚度，在第二区域具有第二厚度，所述第一厚度大于所述第二厚度; 所述半导体图案设置在所述第一区域中的所述栅极绝缘层上，所述半导体图案的端部相对于所述栅极绝缘层具有阶梯部分; 设置在所述半导体图案上的欧姆接触图案，所述欧姆接触图案的与沟道部分相对的端部与所述半导体图案的端部对准; 以及设置在欧姆接触图案上的源极和漏极，源极和漏极彼此间隔开并且包括第一和第二薄膜晶体管图案。

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