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1. 发明申请

US20130092977A1 POWER SEMICONDUCTOR DIODE, IGBT, AND METHOD FOR MANUFACTURING THEREOF 有权
标题翻译：功率半导体二极管，IGBT及其制造方法
公开(公告)号：US20130092977A1
公开(公告)日：2013-04-18
申请号：US13274411
申请日：2011-10-17
申请人： Holger Huesken , Anton Mauder , Hans-Joachim Schulze , Wolfgang Roesner
发明人： Holger Huesken , Anton Mauder , Hans-Joachim Schulze , Wolfgang Roesner
IPC分类号： H01L29/739 , H01L21/331 , H01L29/73
CPC分类号： H01L29/0688 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/08 , H01L29/1608 , H01L29/161 , H01L29/2003 , H01L29/22 , H01L29/36 , H01L29/66128 , H01L29/66143 , H01L29/66325 , H01L29/7393 , H01L29/7395 , H01L29/861 , H01L29/8611 , H01L29/872
摘要： A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.
摘要翻译：提供功率半导体二极管。功率半导体二极管包括具有第一导电类型的第一发射极区域，第二导电类型的第二发射极区域和布置在第一发射极区域和第二发射极区域之间的第一导电类型的漂移区域的半导体衬底。漂移区域与第二发射极区域形成pn结。第一发射极金属化与第一发射极区域接触。第一发射极区域包括第一导电类型的第一掺杂区域和第一导电类型的第二掺杂区域。第一掺杂区与第一发射极金属化形成欧姆接触，第二掺杂区与第一发射极金属化形成非欧姆接触。第二发射极金属化与第二发射极区域接触。

2. 发明授权

US08809902B2 Power semiconductor diode, IGBT, and method for manufacturing thereof 有权
标题翻译：功率半导体二极管，IGBT及其制造方法
公开(公告)号：US08809902B2
公开(公告)日：2014-08-19
申请号：US13274411
申请日：2011-10-17
申请人： Holger Huesken , Anton Mauder , Hans-Joachim Schulze , Wolfgang Roesner
发明人： Holger Huesken , Anton Mauder , Hans-Joachim Schulze , Wolfgang Roesner
IPC分类号： H01L29/739
CPC分类号： H01L29/0688 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/08 , H01L29/1608 , H01L29/161 , H01L29/2003 , H01L29/22 , H01L29/36 , H01L29/66128 , H01L29/66143 , H01L29/66325 , H01L29/7393 , H01L29/7395 , H01L29/861 , H01L29/8611 , H01L29/872
摘要： A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.
摘要翻译：提供功率半导体二极管。功率半导体二极管包括具有第一导电类型的第一发射极区域，第二导电类型的第二发射极区域和布置在第一发射极区域和第二发射极区域之间的第一导电类型的漂移区域的半导体衬底。漂移区域与第二发射极区域形成pn结。第一发射极金属化与第一发射极区域接触。第一发射极区域包括第一导电类型的第一掺杂区域和第一导电类型的第二掺杂区域。第一掺杂区与第一发射极金属化形成欧姆接触，第二掺杂区与第一发射极金属化形成非欧姆接触。第二发射极金属化与第二发射极区域接触。

3. 发明授权

US07112868B2 IGBT with monolithic integrated antiparallel diode 有权
标题翻译： IGBT采用单片集成反并联二极管
公开(公告)号：US07112868B2
公开(公告)日：2006-09-26
申请号：US10698082
申请日：2003-10-30
申请人： Armin Willmeroth , Hans-Joachim Schulze , Holger Huesken , Erich Griebl
发明人： Armin Willmeroth , Hans-Joachim Schulze , Holger Huesken , Erich Griebl
IPC分类号： H01L29/732
CPC分类号： H01L29/861 , H01L29/0696 , H01L29/0834 , H01L29/7395 , H01L2224/0603 , H01L2224/4903 , H01L2924/13055 , H01L2924/00
摘要： An IGBT with monolithic integrated antiparallel diode has one or more emitter short regions forming the diode cathode in the region of the high-voltage edge. The p-type emitter regions of the IGBT have no emitter shorts. The counterelectrode of the diode exclusively comprises p-type semiconductor wells on the front side of the device. Particularly in applications, such as lamp ballast, in which the diode of the IGBT is firstly forward-biased, hard commutation is not effected and the current reversal takes place relatively slowly. The emitter short regions may be strips or points below the high-voltage edge. The horizontal bulk resistance is increased and the snapback effect is reduced without reducing the robustness in the edge region. In a second embodiment, the IGBT is produced using thin wafer technology and the thickness of the substrate defining the inner zone is less than 200 μm. The thickness of the emitter region or of the emitter regions and short region(s) is less than 1 μm. A transparent emitter is preferable in this case.
摘要翻译：具有单片集成反并联二极管的IGBT具有在高压边缘的区域中形成二极管阴极的一个或多个发射极短路区域。 IGBT的p型发射极区域没有发射极短路。二极管的反电极仅在器件前侧包含p型半导体阱。特别是在其中IGBT的二极管首先被正向偏置的诸如灯镇流器的应用中，不会进行硬换向，并且电流反转相对缓慢地发生。发射极短区域可以是高压边缘以下的条带或点。水平体积电阻增加，并且在不降低边缘区域的鲁棒性的情况下降低了回弹效应。在第二实施例中，使用薄晶片技术制造IGBT，并且限定内部区域的衬底的厚度小于200μm。发射极区域或发射极区域和短区域的厚度小于1um。在这种情况下，优选透明发光体。

4. 发明授权

US09245760B2 Methods of forming epitaxial layers on a porous semiconductor layer 有权
标题翻译：在多孔半导体层上形成外延层的方法
公开(公告)号：US09245760B2
公开(公告)日：2016-01-26
申请号：US12895664
申请日：2010-09-30
申请人： Anton Mauder , Hans-Joachim Schulze , Hans-Joerg Timme , Franz Hirler , Francisco Javier Santos Rodriguez
发明人： Anton Mauder , Hans-Joachim Schulze , Hans-Joerg Timme , Franz Hirler , Francisco Javier Santos Rodriguez
IPC分类号： H01L21/20 , H01L21/306 , H01L21/02 , H01L21/78 , H01L29/78
CPC分类号： H01L29/2003 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02513 , H01L21/02521 , H01L21/02532 , H01L21/0254 , H01L21/0262 , H01L21/306 , H01L21/30621 , H01L21/3065 , H01L21/324 , H01L21/78 , H01L29/045 , H01L29/45 , H01L29/7846 , H01L29/7848
摘要： In one embodiment, a method of forming a semiconductor device includes forming a first porous semiconductor layer over a top surface of a substrate. A first epitaxial layer is formed over the first porous semiconductor layer. A circuitry is formed within and over the first epitaxial layer. The circuitry is formed without completely oxidizing the first epitaxial layer.
摘要翻译：在一个实施例中，形成半导体器件的方法包括在衬底的顶表面上形成第一多孔半导体层。在第一多孔半导体层上形成第一外延层。在第一外延层内和上方形成电路。在不完全氧化第一外延层的情况下形成电路。

5. 发明授权

US08829584B2 Semiconductor device with a dynamic gate-drain capacitance 有权
标题翻译：具有动态栅极 - 漏极电容的半导体器件
公开(公告)号：US08829584B2
公开(公告)日：2014-09-09
申请号：US13614479
申请日：2012-09-13
申请人： Anton Mauder , Hans-Joachim Schulze , Carolin Tolksdorf , Winfried Kaindl , Armin Willmeroth
发明人： Anton Mauder , Hans-Joachim Schulze , Carolin Tolksdorf , Winfried Kaindl , Armin Willmeroth
IPC分类号： H01L27/07
CPC分类号： H01L27/0808 , H01L21/26513 , H01L27/0811 , H01L27/088 , H01L29/7836
摘要： A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage.
摘要翻译：具有动态栅极漏极电容的半导体器件。一个实施例提供一种半导体器件。该器件包括半导体衬底，场效应晶体管结构，其包括源区，第一体区，漏区，栅电极结构和栅极绝缘层。栅极绝缘层设置在栅电极结构和体区之间。栅极电极结构和漏极区域部分地形成电容器结构，其包括栅极 - 漏极电容，该栅极 - 漏极电容被配置为随着施加在源极和漏极区域之间的变化的反向电压而动态地栅极 - 漏极电容在给定的阈值下包括至少一个局部最大值，或者在给定的反向电压下包括平台状过程。

6. 发明授权

US08822306B2 Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core 有权
标题翻译：具有石墨芯的复合晶片的制造方法以及具有石墨芯的复合晶片
公开(公告)号：US08822306B2
公开(公告)日：2014-09-02
申请号：US13206029
申请日：2011-08-09
申请人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze , Karsten Kellermann , Michael Sommer , Christian Rottmair , Roland Rupp
发明人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze , Karsten Kellermann , Michael Sommer , Christian Rottmair , Roland Rupp
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , C30B25/186 , H01L21/02115 , H01L21/02282 , H01L21/02598 , H01L21/2007 , H01L21/265 , H01L21/3212 , H01L21/324 , H01L21/76251 , H01L29/1608 , H01L29/20 , H01L29/2003
摘要： According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.
摘要翻译：根据实施例，复合晶片包括具有石墨层和附着到载体衬底的单晶半导体层的载体衬底。

7. 发明申请

US20140042595A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING GRINDING FROM A BACK SURFACE AND SEMICONDUCTOR DEVICE 有权
标题翻译：制造包括从背面和半导体器件研磨的半导体器件的方法
公开(公告)号：US20140042595A1
公开(公告)日：2014-02-13
申请号：US13571769
申请日：2012-08-10
申请人： Hans-Joachim Schulze , Anton Mauder
发明人： Hans-Joachim Schulze , Anton Mauder
IPC分类号： H01L29/02 , H01L21/78
CPC分类号： H01L29/06 , B24B7/228 , B24B37/013 , B24B37/042 , H01L21/302 , H01L21/304 , H01L21/30625 , H01L21/3247 , H01L21/764 , H01L21/78 , H01L22/26 , H01L29/66333
摘要： A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.
摘要翻译：将腔从前表面刻蚀成半导体衬底。在腔的底部提供蚀刻停止结构之后，空腔被关闭。从与前表面相对的后表面，半导体衬底至少被研磨到定向到后表面的蚀刻停止结构的边缘。在蚀刻腔的底部提供蚀刻停止结构允许精确地调节半导体器件的半导体本体的厚度。

8. 发明申请

US20140001514A1 Semiconductor Device and Method for Producing a Doped Semiconductor Layer 审中-公开
标题翻译：用于制造掺杂半导体层的半导体器件和方法
公开(公告)号：US20140001514A1
公开(公告)日：2014-01-02
申请号：US13539944
申请日：2012-07-02
申请人： Hans-Joachim Schulze , Franz Hirler , Anton Mauder , Helmut Strack , Frank Kahlmann , Gerhard Miller
发明人： Hans-Joachim Schulze , Franz Hirler , Anton Mauder , Helmut Strack , Frank Kahlmann , Gerhard Miller
IPC分类号： H01L29/36 , H01L21/225
CPC分类号： H01L29/66348 , H01L21/2205 , H01L21/2658 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0878 , H01L29/102 , H01L29/1095 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/7397 , H01L29/7428 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/7816 , H01L29/861 , H01L29/872
摘要： A semiconductor device includes a device region. The device region includes at least one device region section including dopant atoms of a first doping type and with a first doping concentration of at least 1E16 cm−3 and dopant atoms of a second doping type and with a second doping concentration of at least 1E16 cm−3.
摘要翻译：半导体器件包括器件区域。器件区域包括至少一个器件区域部分，其包括第一掺杂类型的掺杂剂原子和具有至少1E16cm-3的第一掺杂浓度和第二掺杂类型的掺杂剂原子，并且具有至少1E16cm的第二掺杂浓度 -3。

9. 发明授权

US08614478B2 Method for protecting a semiconductor device against degradation, a semiconductor device protected against hot charge carriers and a manufacturing method therefor 有权
标题翻译：防止半导体器件劣化的方法，保护热电荷载流子的半导体器件及其制造方法
公开(公告)号：US08614478B2
公开(公告)日：2013-12-24
申请号：US12843326
申请日：2010-07-26
申请人： Anton Mauder , Hans-Joachim Schulze
发明人： Anton Mauder , Hans-Joachim Schulze
IPC分类号： H01L29/66
CPC分类号： H01L29/407 , H01L21/283 , H01L29/063 , H01L29/0878 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/7393 , H01L29/7394 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/7835 , H01L29/792
摘要： A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided.
摘要翻译：提供了一种用于保护半导体器件免于其电特性劣化的方法。该方法包括提供具有形成介电半导体界面的第一半导体区域和带电介质层的半导体器件。第一半导体区域的多数电荷载流子是第一电荷类型。带电电介质层包括第一充电类型的固定电荷。固定电荷的每个面积的电荷载流子密度被配置为使得带电电介质层被屏蔽，以阻止在第一半导体区域中产生的热多数电荷载流子。此外，提供了防止热电荷载流子的半导体器件和形成半导体器件的方法。

10. 发明授权

US08461648B2 Semiconductor component with a drift region and a drift control region 有权
公开(公告)号：US08461648B2
公开(公告)日：2013-06-11
申请号：US11996906
申请日：2006-07-27
申请人： Frank Pfirsch , Anton Mauder , Armin Willmeroth , Hans-Joachim Schulze , Stefan Sedlmaier , Markus Zundel , Franz Hirler , Arunjai Mittal
发明人： Frank Pfirsch , Anton Mauder , Armin Willmeroth , Hans-Joachim Schulze , Stefan Sedlmaier , Markus Zundel , Franz Hirler , Arunjai Mittal
IPC分类号： H01L29/732
CPC分类号： H01L29/7803 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/4916 , H01L29/66734 , H01L29/7802 , H01L29/7804 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： A semiconductor component with a drift region and a drift control region. One embodiment includes a semiconductor body having a drift region of a first conduction type in the semiconductor body. A drift control region composed of a semiconductor material, which is arranged, at least in sections, is adjacent to the drift region in the semiconductor body. An accumulation dielectric is arranged between the drift region and the drift control region.

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