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1. 发明申请

US20090225900A1 DATA TRANSMITTING CIRCUIT AND TRANSMITTING METHOD 有权
标题翻译：数据发送电路和发送方法
公开(公告)号：US20090225900A1
公开(公告)日：2009-09-10
申请号：US12392140
申请日：2009-02-25
申请人： Hisakatsu YAMAGUCHI , Yoshiyasu Doi , Hirotaka Tamura
发明人： Hisakatsu YAMAGUCHI , Yoshiyasu Doi , Hirotaka Tamura
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04B3/23
摘要： A data transmitting circuit includes a reflection suppressive component generating circuit for generating a reflection suppressive component for suppressing the reflection caused by the discontinuity in the characteristic impedance on a transmission line, and a data output circuit for amplifying the reflection suppressive component and the data to be currently transmitted to a receiving side and outputting them to the transmission line.
摘要翻译：数据发送电路包括：反射抑制分量产生电路，用于产生用于抑制由传输线上的特性阻抗的不连续性引起的反射的反射抑制分量;以及数据输出电路，用于放大反射抑制分量和数据当前发送到接收侧并将其输出到传输线。

2. 发明申请

US20090220029A1 CLOCK RECOVERY CIRCUIT AND DATA RECEIVING CIRCUIT 有权
标题翻译：时钟恢复电路和数据接收电路
公开(公告)号：US20090220029A1
公开(公告)日：2009-09-03
申请号：US12400360
申请日：2009-03-09
申请人： Hisakatsu YAMAGUCHI , Hirotaka Tamura
发明人： Hisakatsu YAMAGUCHI , Hirotaka Tamura
IPC分类号： H04L27/00
CPC分类号： H03L7/091 , G11C7/1078 , G11C7/1087 , G11C7/222 , H04L7/0331
摘要： A clock recovery circuit has a boundary detection circuit detecting a boundary in an input signal in accordance with a first signal, and performs recovery of a clock by controlling the timing of the first signal in accordance with the detected boundary. The clock recovery circuit has a boundary detection timing varying circuit and a variation reducing circuit. The boundary detection timing varying circuit dynamically varies boundary detection timing in the boundary detection circuit by applying a variation to the first signal, and the variation reducing circuit reduces a phase variation occurring in the recovered clock in accordance with the dynamic variation of the boundary detection timing performed by the boundary detection timing varying circuit.
摘要翻译：时钟恢复电路具有根据第一信号检测输入信号中的边界的边界检测电路，并且根据检测到的边界通过控制第一信号的定时来执行时钟的恢复。时钟恢复电路具有边界检测定时改变电路和变化减小电路。边界检测定时变化电路通过对第一信号施加变化动态地改变边界检测电路中的边界检测定时，并且变化减小电路根据边界检测定时的动态变化减少在恢复的时钟中发生的相位变化由边界检测定时变化电路执行。

3. 发明申请

US20090309771A1 DATA TRANSMISSION CIRCUIT AND DATA COMMUNICATION SYSTEM 有权
标题翻译：数据传输电路和数据通信系统
公开(公告)号：US20090309771A1
公开(公告)日：2009-12-17
申请号：US12546166
申请日：2009-08-24
申请人： Hisakatsu YAMAGUCHI
发明人： Hisakatsu YAMAGUCHI
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A data transmission circuit that converts parallel data signals into a serial data signal to transmit the serial data signal includes a clock generation circuit, an output circuit, and a shift register circuit for securely conducting data communication among internal elements regardless of the improvement in data transfer rate, the increase in manufacturing variance, the variation in power supply voltage and temperature, and the like. The clock generation circuit generates a clock signal. The output circuit is provided to output the serial data signal. The shift register circuit acquires the parallel data signals and sequentially transfers the acquired parallel data signals to the output circuit in a bitwise manner with the use of a shift operation synchronized with the clock signal from the clock generation circuit.
摘要翻译：将并行数据信号转换为串行数据信号以发送串行数据信号的数据传输电路包括时钟产生电路，输出电路和移位寄存器电路，用于在内部元件之间安全地进行数据通信，而不管数据传输的改进速率，制造方差的增加，电源电压和温度的变化等。时钟发生电路产生时钟信号。提供输出电路以输出串行数据信号。移位寄存器电路获取并行数据信号，并且通过使用与来自时钟产生电路的时钟信号同步的移位操作，以逐位方式将获取的并行数据信号顺序地传送到输出电路。

4. 发明申请

US20090027091A1 CLOCK FREQUENCY DIVIDING CIRCUIT 有权
标题翻译：时钟分频电路
公开(公告)号：US20090027091A1
公开(公告)日：2009-01-29
申请号：US12199168
申请日：2008-08-27
申请人： Hisakatsu YAMAGUCHI , Kouichi KANDA , Junji OGAWA , Hirotaka TAMURA
发明人： Hisakatsu YAMAGUCHI , Kouichi KANDA , Junji OGAWA , Hirotaka TAMURA
IPC分类号： H03B19/06
CPC分类号： H03K27/00 , H03B5/1203 , H03B5/1228 , H03B5/1243 , H03B19/00
摘要： A first frequency dividing circuit and a second frequency dividing circuit are provided, and these circuits frequency-divide two-phase external clocks injected from an external part, to output four-phase clocks with phase guarantee. Each of the frequency dividing circuits includes a mixer, an adding circuit, and a phase circuit. The first frequency dividing circuit and the second frequency dividing circuit are coupled in loop shape via a first coupling circuit and a second coupling circuit. The first coupling circuit receives a first output signal of the first frequency dividing circuit to output a second external input signal to the second frequency dividing circuit, and the second coupling circuit receives a second output signal of the second frequency dividing circuit to output a first external input signal to the first frequency dividing circuit, and a clock frequency dividing circuit with a high loop gain and a wide lock range can be realized.
摘要翻译：提供第一分频电路和第二分频电路，这些电路对从外部部分注入的两相外部时钟进行分频，以输出具有相位保证的四相时钟。每个分频电路包括混频器，加法电路和相电路。第一分频电路和第二分频电路经由第一耦合电路和第二耦合电路以环形形式耦合。第一耦合电路接收第一分频电路的第一输出信号，以将第二外部输入信号输出到第二分频电路，第二耦合电路接收第二分频电路的第二输出信号，以输出第一外部输入信号到第一分频电路，并且可以实现具有高环路增益和宽锁定范围的时钟分频电路。

5. 发明申请

US20100127906A1 DATA RECOVERY CIRCUIT, DATA RECOVERY METHOD AND DATA RECEIVING APPARATUS 有权
标题翻译：数据恢复电路，数据恢复方法和数据接收装置
公开(公告)号：US20100127906A1
公开(公告)日：2010-05-27
申请号：US12621616
申请日：2009-11-19
申请人： Hisakatsu YAMAGUCHI , Hirotaka Tamura , Masaya Kibune
发明人： Hisakatsu YAMAGUCHI , Hirotaka Tamura , Masaya Kibune
IPC分类号： H03M1/20 , H03M1/12
CPC分类号： H04L7/0334
摘要： A data recovery circuit includes an analog-digital converter creating a digital code sequence, a phase detector calculating a position of a crossing point from the digital code sequence, a phase estimator acquiring a presumed position of a data center point of a data sequence based on the position of the crossing point, and a data determining circuit extracting the sequence of data determination values from the digital code sequence based on the position of the crossing point and the presumed position of the data center point.
摘要翻译：数据恢复电路包括产生数字码序列的模拟数字转换器，从数字码序列计算交叉点的位置的相位检测器，基于数据序列的数据中心点的推定位置的相位估计器，基于交叉点的位置，以及数据确定电路，基于交叉点的位置和数据中心点的假设位置，从数字码序列中提取数据确定值的序列。

6. 发明申请

US20090066394A1 PEAKING CONTROL CIRCUIT 有权
标题翻译：扬声器控制电路
公开(公告)号：US20090066394A1
公开(公告)日：2009-03-12
申请号：US12239542
申请日：2008-09-26
申请人： Kouichi KANDA , Hirotaka TAMURA , Hisakatsu YAMAGUCHI , Junji OGAWA
发明人： Kouichi KANDA , Hirotaka TAMURA , Hisakatsu YAMAGUCHI , Junji OGAWA
IPC分类号： H03L5/00
CPC分类号： H03K5/12 , H03F1/42 , H03F3/45183 , H03F3/45632 , H03F2200/36 , H03F2200/435 , H03F2200/447 , H03F2203/45631 , H03F2203/45638 , H03F2203/45681 , H03F2203/45686 , H03H11/1213 , H03H11/1291 , H04L25/028 , H04L25/0288
摘要： There are provided a peaking detection part detecting a peaking amount in an output part of an inductor peaking circuit and a control signal generation part varying a circuit parameter of the inductor peaking circuit based on the peaking amount detected by the peaking detection part. Particularly, the inductor peaking circuit has inductors and resistors inserted in series between the output part and a power supply, and capacitances coupled in parallel between the output part and an earth (GND), and depending on respective values of these inductors, resistors and capacitances, it is possible to suppress a peaking generated in the output part.
摘要翻译：提供了一种检测电感器峰值电路的输出部分中的峰值量的峰值检测部分和基于由峰值检测部分检测到的峰化量来改变电感器峰值电路的电路参数的控制信号产生部分。特别地，电感器峰值电路具有串联插入在输出部分和电源之间的电感器和电阻器，以及在输出部分和地（GND）之间并联耦合的电容，并且取决于这些电感器，电阻器和电容的相应值，可以抑制在输出部分中产生的峰值。

7. 发明申请

US20110299583A1 RECEIVING DEVICE AND RECEIVING METHOD 有权
标题翻译：接收设备和接收方法
公开(公告)号：US20110299583A1
公开(公告)日：2011-12-08
申请号：US13071205
申请日：2011-03-24
申请人： Hisakatsu YAMAGUCHI , Yasumoto Tomita , Satoshi Kawahara
发明人： Hisakatsu YAMAGUCHI , Yasumoto Tomita , Satoshi Kawahara
IPC分类号： H03H7/40
CPC分类号： H04B3/12 , H03H11/245
摘要： To optimize an adaptive equalizer with a simple controlling circuit, the receiving device includes a number counting part counting, in a range of detection having a predetermined width, a sampling result corresponding to the input signal being shaped by an equalizer circuit at a determination timing indicated by a clock signal obtained in a CDR circuit, a zone scanning part scanning the range of detection in a scanning zone including a variation range of the input signal; a coefficient altering part altering an equalizer coefficient set to the equalizer circuit; a peak detecting part detecting a peak value of a number of appearances of the sampling result according to alteration of the equalizer coefficient and scanning of the range of detection; and a coefficient specifying part specifying the equalizer coefficient being used when detecting the peak value in the peak detecting part as a first coefficient.
摘要翻译：为了利用简单的控制电路来优化自适应均衡器，接收装置包括在具有预定宽度的检测范围内计数对应于输入信号的采样结果的数量计数部件，其在所指示的确定时刻由均衡器电路整形通过在CDR电路中获得的时钟信号，区域扫描部分扫描包括输入信号的变化范围的扫描区域中的检测范围; 系数改变部分，改变设定到均衡器电路的均衡器系数; 峰值检测部分，根据均衡器系数的改变和检测范围的扫描来检测采样结果的出现次数的峰值; 以及系数指定部，其在检测峰值检测部中的峰值时作为第一系数，指定使用的均衡器系数。

8. 发明申请

US20100040130A1 RECEIVER CIRCUIT 有权
标题翻译：接收电路
公开(公告)号：US20100040130A1
公开(公告)日：2010-02-18
申请号：US12561917
申请日：2009-09-17
申请人： Hisakatsu YAMAGUCHI
发明人： Hisakatsu YAMAGUCHI
IPC分类号： H04L27/01
CPC分类号： H04B3/145 , H04L7/033 , H04L25/0272 , H04L25/0292 , H04L25/03885
摘要： A first phase adjustment circuit adjusts phases of a data decision clock signal and a first boundary decision clock signal according to a phase adjustment amount based on an output signal of a data decision circuit and an output signal of a first boundary decision circuit. A second phase adjustment circuit adjusts a phase of a second boundary decision clock signal according to a result of adding the phase adjustment amount and a phase adjustment amount offset. An adaptive equalization control circuit adjusts an equalization coefficient of an equalization circuit according to a data width of an output signal of the equalization circuit based on a logical comparison result between the output signal of the data decision circuit and an output signal of a second boundary decision circuit when the phase adjustment amount offset is changed.
摘要翻译：第一相位调整电路根据数据判定电路的输出信号和第一边界判定电路的输出信号，根据相位调整量来调整数据判定时钟信号和第一边界判定时钟信号的相位。第二相位调整电路根据相位调整量和相位调整量偏移的结果，调整第二边界判定时钟信号的相位。自适应均衡控制电路根据数据判定电路的输出信号与第二边界判定的输出信号之间的逻辑比较结果，根据均衡电路的输出信号的数据宽度来调整均衡电路的均衡系数当相位调整量偏移改变时，电路。

9. 发明申请

US20090310666A1 ADAPTIVE EQUALIZER CIRCUIT 有权
标题翻译：自适应均衡器电路
公开(公告)号：US20090310666A1
公开(公告)日：2009-12-17
申请号：US12543109
申请日：2009-08-18
申请人： Hisakatsu YAMAGUCHI , Shunichiro Masaki , Hideki Ishida , Kohtaroh Gotoh
发明人： Hisakatsu YAMAGUCHI , Shunichiro Masaki , Hideki Ishida , Kohtaroh Gotoh
IPC分类号： H03H7/40 , H03K5/159
CPC分类号： H04L25/03885 , H04B3/145
摘要： An adaptive equalizer circuit includes an equalizer circuit configured to produce an output data signal in response to an equalizing factor, a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing, a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½ unit time away from the predetermined timing, and a control unit configured to detect, multiple times, a pattern having consecutive data items of a first value followed by a data item of a second value, and to adjust the equalizing factor such that a data detection value and a boundary detection value obtained for the data item of the second value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.
摘要翻译：自适应均衡器电路包括：均衡器电路，被配置为响应于均衡因素产生输出数据信号;数据检测电路，被配置为在预定定时在给定的单位时间内检测输出数据信号的信号电平;边界检测电路被配置为在距所述预定定时的1/2单位时间的定时检测所述输出数据信号的信号电平;以及控制单元，被配置为多次检测具有第一值的数据的后续数据的模式，项目，并且调整均衡因子，使得对于第二值的数据项获得的数据检测值和边界检测值彼此相等一定百分比，并且基本上彼此不同相同百分比的时间。

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