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1. 发明授权

US08588340B2 Receiving device 有权
标题翻译：接收设备
公开(公告)号：US08588340B2
公开(公告)日：2013-11-19
申请号：US13153195
申请日：2011-06-03
申请人： Yasumoto Tomita , Hisakatsu Yamaguchi , Satoshi Kawahara
发明人： Yasumoto Tomita , Hisakatsu Yamaguchi , Satoshi Kawahara
IPC分类号： H03K9/00 , H04L27/00
CPC分类号： H04L25/03057
摘要： To optimize an adaptive equalizer with a simple controlling circuit, the receiving device includes a number counting part counting, in a range of detection having a predetermined width, a sampling result corresponding to the input signal being shaped by an equalizer circuit at a determination timing indicated by a clock signal obtained in a CDR circuit, a zone scanning part scanning the range of detection in a scanning zone including a variation range of the input signal; a coefficient altering part altering an equalizer coefficient set to the equalizer circuit; a peak detecting part detecting a peak value of a number of appearances of the sampling result according to alteration of the equalizer coefficient and scanning of the range of detection; and a coefficient specifying part specifying the equalizer coefficient being used when detecting the peak value in the peak detecting part as a first coefficient.
摘要翻译：为了利用简单的控制电路来优化自适应均衡器，接收装置包括在具有预定宽度的检测范围内计数对应于输入信号的采样结果的数量计数部件，其在所指示的确定时刻由均衡器电路整形通过在CDR电路中获得的时钟信号，区域扫描部分扫描包括输入信号的变化范围的扫描区域中的检测范围; 系数改变部分，改变设定到均衡器电路的均衡器系数; 峰值检测部分，根据均衡器系数的改变和检测范围的扫描来检测采样结果的出现次数的峰值; 以及系数指定部，其在检测峰值检测部中的峰值时作为第一系数，指定使用的均衡器系数。

2. 发明申请

US20100202578A1 CLOCK GENERATION CIRCUIT AND SYSTEM 失效
标题翻译：时钟发生电路和系统
公开(公告)号：US20100202578A1
公开(公告)日：2010-08-12
申请号：US12633558
申请日：2009-12-08
申请人： Yasumoto TOMITA , Masaya Kibune , Hirotaka Tamura
发明人： Yasumoto TOMITA , Masaya Kibune , Hirotaka Tamura
IPC分类号： H04L7/00
CPC分类号： H04L7/033 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/091 , H04L7/007 , H04L7/043
摘要： A clock generation circuit includes: a first determination circuit that detects an input signal at a first phase position based on first frequency signal; a second determination circuit that detects the input signal at a second phase position based on second frequency signal; a phase detector that compares output of the first determination circuit and output of the second determination circuit; a first summing circuit which sums comparison result and first control signal; a second summing circuit which sums comparison result and second control signal; a first voltage controlled oscillation circuit which receives output of the first summing circuit and outputs the first frequency signal; a second voltage controlled oscillation circuit which received output of the second summing circuit and outputs the second frequency signal; and a phase adjustment circuit which generates first control signal and second control signal based on first frequency signal and second frequency signal.
摘要翻译：时钟发生电路包括：第一确定电路，其基于第一频率信号检测第一相位位置处的输入信号; 第二确定电路，其基于第二频率信号来检测第二相位位置处的输入信号; 相位检测器，比较第一确定电路的输出和第二确定电路的输出; 第一求和电路，其将比较结果和第一控制信号相加; 第二加法电路，其将比较结果和第二控制信号相加; 第一压控振荡电路，接收第一求和电路的输出并输出第一频率信号; 接收第二加法电路的输出并输出第二频率信号的第二压控振荡电路; 以及基于第一频率信号和第二频率信号产生第一控制信号和第二控制信号的相位调整电路。

3. 发明授权

US08638843B2 Receiving device and receiving method 有权
标题翻译：接收设备和接收方式
公开(公告)号：US08638843B2
公开(公告)日：2014-01-28
申请号：US13071205
申请日：2011-03-24
申请人： Hisakatsu Yamaguchi , Yasumoto Tomita , Satoshi Kawahara
发明人： Hisakatsu Yamaguchi , Yasumoto Tomita , Satoshi Kawahara
IPC分类号： H03H7/40
CPC分类号： H04B3/12 , H03H11/245
摘要： To optimize an adaptive equalizer with a simple controlling circuit, the receiving device includes a number counting part counting, in a range of detection having a predetermined width, a sampling result corresponding to the input signal being shaped by an equalizer circuit at a determination timing indicated by a clock signal obtained in a CDR circuit, a zone scanning part scanning the range of detection in a scanning zone including a variation range of the input signal; a coefficient altering part altering an equalizer coefficient set to the equalizer circuit; a peak detecting part detecting a peak value of a number of appearances of the sampling result according to alteration of the equalizer coefficient and scanning of the range of detection; and a coefficient specifying part specifying the equalizer coefficient being used when detecting the peak value in the peak detecting part as a first coefficient.
摘要翻译：为了利用简单的控制电路来优化自适应均衡器，接收装置包括在具有预定宽度的检测范围内计数对应于输入信号的采样结果的数量计数部件，其在所指示的确定时刻由均衡器电路整形通过在CDR电路中获得的时钟信号，区域扫描部分扫描包括输入信号的变化范围的扫描区域中的检测范围; 系数改变部分，改变设定到均衡器电路的均衡器系数; 峰值检测部分，根据均衡器系数的改变和检测范围的扫描来检测采样结果的出现次数的峰值; 以及系数指定部，其在检测峰值检测部中的峰值时作为第一系数，指定使用的均衡器系数。

4. 发明授权

US08238504B2 Clock generation circuit and system 失效
标题翻译：时钟发生电路和系统
公开(公告)号：US08238504B2
公开(公告)日：2012-08-07
申请号：US12633558
申请日：2009-12-08
申请人： Yasumoto Tomita , Masaya Kibune , Hirotaka Tamura
发明人： Yasumoto Tomita , Masaya Kibune , Hirotaka Tamura
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04L7/033 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/091 , H04L7/007 , H04L7/043
摘要： A clock generation circuit includes: a first determination circuit that detects an input signal at a first phase position based on first frequency signal; a second determination circuit that detects the input signal at a second phase position based on second frequency signal; a phase detector that compares output of the first determination circuit and output of the second determination circuit; a first summing circuit which sums comparison result and first control signal; a second summing circuit which sums comparison result and second control signal; a first voltage controlled oscillation circuit which receives output of the first summing circuit and outputs the first frequency signal; a second voltage controlled oscillation circuit which received output of the second summing circuit and outputs the second frequency signal; and a phase adjustment circuit which generates first control signal and second control signal based on first frequency signal and second frequency signal.
摘要翻译：时钟发生电路包括：第一确定电路，其基于第一频率信号检测第一相位位置处的输入信号; 第二确定电路，其基于第二频率信号来检测第二相位位置处的输入信号; 相位检测器，比较第一确定电路的输出和第二确定电路的输出; 第一求和电路，其将比较结果和第一控制信号相加; 第二加法电路，其将比较结果和第二控制信号相加; 第一压控振荡电路，接收第一求和电路的输出并输出第一频率信号; 接收第二加法电路的输出并输出第二频率信号的第二压控振荡电路; 以及基于第一频率信号和第二频率信号产生第一控制信号和第二控制信号的相位调整电路。

5. 发明申请

US20110299585A1 RECEIVING DEVICE AND RECEIVING METHOD 有权
公开(公告)号：US20110299585A1
公开(公告)日：2011-12-08
申请号：US13153195
申请日：2011-06-03
申请人： Yasumoto TOMITA , Hisakatsu Yamaguchi , Satoshi Kawahara
发明人： Yasumoto TOMITA , Hisakatsu Yamaguchi , Satoshi Kawahara
IPC分类号： H04L27/01
CPC分类号： H04L25/03057
摘要： To optimize an adaptive equalizer with a simple controlling circuit, the receiving device includes a number counting part counting, in a range of detection having a predetermined width, a sampling result corresponding to the input signal being shaped by an equalizer circuit at a determination timing indicated by a clock signal obtained in a CDR circuit, a zone scanning part scanning the range of detection in a scanning zone including a variation range of the input signal; a coefficient altering part altering an equalizer coefficient set to the equalizer circuit; a peak detecting part detecting a peak value of a number of appearances of the sampling result according to alteration of the equalizer coefficient and scanning of the range of detection; and a coefficient specifying part specifying the equalizer coefficient being used when detecting the peak value in the peak detecting part as a first coefficient.

6. 发明申请

US20110299583A1 RECEIVING DEVICE AND RECEIVING METHOD 有权
标题翻译：接收设备和接收方法
公开(公告)号：US20110299583A1
公开(公告)日：2011-12-08
申请号：US13071205
申请日：2011-03-24
申请人： Hisakatsu YAMAGUCHI , Yasumoto Tomita , Satoshi Kawahara
发明人： Hisakatsu YAMAGUCHI , Yasumoto Tomita , Satoshi Kawahara
IPC分类号： H03H7/40
CPC分类号： H04B3/12 , H03H11/245
摘要： To optimize an adaptive equalizer with a simple controlling circuit, the receiving device includes a number counting part counting, in a range of detection having a predetermined width, a sampling result corresponding to the input signal being shaped by an equalizer circuit at a determination timing indicated by a clock signal obtained in a CDR circuit, a zone scanning part scanning the range of detection in a scanning zone including a variation range of the input signal; a coefficient altering part altering an equalizer coefficient set to the equalizer circuit; a peak detecting part detecting a peak value of a number of appearances of the sampling result according to alteration of the equalizer coefficient and scanning of the range of detection; and a coefficient specifying part specifying the equalizer coefficient being used when detecting the peak value in the peak detecting part as a first coefficient.
摘要翻译：为了利用简单的控制电路来优化自适应均衡器，接收装置包括在具有预定宽度的检测范围内计数对应于输入信号的采样结果的数量计数部件，其在所指示的确定时刻由均衡器电路整形通过在CDR电路中获得的时钟信号，区域扫描部分扫描包括输入信号的变化范围的扫描区域中的检测范围; 系数改变部分，改变设定到均衡器电路的均衡器系数; 峰值检测部分，根据均衡器系数的改变和检测范围的扫描来检测采样结果的出现次数的峰值; 以及系数指定部，其在检测峰值检测部中的峰值时作为第一系数，指定使用的均衡器系数。

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