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1. 发明申请

US20090310666A1 ADAPTIVE EQUALIZER CIRCUIT 有权
标题翻译：自适应均衡器电路
公开(公告)号：US20090310666A1
公开(公告)日：2009-12-17
申请号：US12543109
申请日：2009-08-18
申请人： Hisakatsu YAMAGUCHI , Shunichiro Masaki , Hideki Ishida , Kohtaroh Gotoh
发明人： Hisakatsu YAMAGUCHI , Shunichiro Masaki , Hideki Ishida , Kohtaroh Gotoh
IPC分类号： H03H7/40 , H03K5/159
CPC分类号： H04L25/03885 , H04B3/145
摘要： An adaptive equalizer circuit includes an equalizer circuit configured to produce an output data signal in response to an equalizing factor, a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing, a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½ unit time away from the predetermined timing, and a control unit configured to detect, multiple times, a pattern having consecutive data items of a first value followed by a data item of a second value, and to adjust the equalizing factor such that a data detection value and a boundary detection value obtained for the data item of the second value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.
摘要翻译：自适应均衡器电路包括：均衡器电路，被配置为响应于均衡因素产生输出数据信号;数据检测电路，被配置为在预定定时在给定的单位时间内检测输出数据信号的信号电平;边界检测电路被配置为在距所述预定定时的1/2单位时间的定时检测所述输出数据信号的信号电平;以及控制单元，被配置为多次检测具有第一值的数据的后续数据的模式，项目，并且调整均衡因子，使得对于第二值的数据项获得的数据检测值和边界检测值彼此相等一定百分比，并且基本上彼此不同相同百分比的时间。

2. 发明授权

US08270462B2 Adaptive equalizer circuit 有权
标题翻译：自适应均衡器电路
公开(公告)号：US08270462B2
公开(公告)日：2012-09-18
申请号：US12543109
申请日：2009-08-18
申请人： Hisakatsu Yamaguchi , Shunichiro Masaki , Hideki Ishida , Kohtaroh Gotoh
发明人： Hisakatsu Yamaguchi , Shunichiro Masaki , Hideki Ishida , Kohtaroh Gotoh
IPC分类号： H03H7/30
CPC分类号： H04L25/03885 , H04B3/145
摘要： An adaptive equalizer circuit includes an equalizer circuit configured to produce an output data signal in response to an equalizing factor, a data detecting circuit configured to detect a signal level of the output data signal in a given unit time at predetermined timing, a boundary detecting circuit configured to detect a signal level of the output data signal at a timing that is ½ unit time away from the predetermined timing, and a control unit configured to detect, multiple times, a pattern having consecutive data items of a first value followed by a data item of a second value, and to adjust the equalizing factor such that a data detection value and a boundary detection value obtained for the data item of the second value are equal to each other a certain percentage of times, and are different from each other substantially the same percentage of times.
摘要翻译：自适应均衡器电路包括：均衡器电路，被配置为响应于均衡因素产生输出数据信号;数据检测电路，被配置为在预定定时在给定的单位时间内检测输出数据信号的信号电平;边界检测电路被配置为在距所述预定定时的1/2单位时间的定时检测所述输出数据信号的信号电平;以及控制单元，被配置为多次检测具有第一值的数据的后续数据的模式，项目，并且调整均衡因子，使得对于第二值的数据项获得的数据检测值和边界检测值彼此相等一定百分比，并且基本上彼此不同相同百分比的时间。

3. 发明申请

US20090195281A1 Timing Signal Generating Circuit, Semiconductor Integrated Circuit Device and Semiconductor Integrated Circuit System to which the Timing Signal Generating Circuit is Applied, and Signal Transmission System 有权
标题翻译：定时信号发生电路，应用了定时信号发生电路的半导体集成电路装置和半导体集成电路系统以及信号传输系统
公开(公告)号：US20090195281A1
公开(公告)日：2009-08-06
申请号：US12358861
申请日：2009-01-23
申请人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
发明人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
IPC分类号： H03L7/00
CPC分类号： H04L7/0337 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03K2005/00052 , H04L7/0025
摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
摘要翻译：半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

4. 发明授权

US08065553B2 Phase interpolator for a timing signal generating circuit 有权
标题翻译：用于定时信号发生电路的相位内插器
公开(公告)号：US08065553B2
公开(公告)日：2011-11-22
申请号：US12358861
申请日：2009-01-23
申请人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
发明人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
IPC分类号： G06F1/04 , G06F1/12 , G06F1/24 , H03J7/04
CPC分类号： H04L7/0337 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03K2005/00052 , H04L7/0025
摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
摘要翻译：半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

5. 发明授权

US07496781B2 Timing signal generating circuit with a master circuit and slave circuits 有权
标题翻译：具有主电路和从电路的定时信号发生电路
公开(公告)号：US07496781B2
公开(公告)日：2009-02-24
申请号：US10278800
申请日：2002-10-24
申请人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
发明人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
IPC分类号： G06F1/04 , G05F1/12 , H03L7/06
CPC分类号： H04L7/0337 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03K2005/00052 , H04L7/0025
摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
摘要翻译：半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

6. 发明授权

US07116744B2 Clock recovery circuit and receiver circuit for improving the error rate of signal reproduction 有权
公开(公告)号：US07116744B2
公开(公告)日：2006-10-03
申请号：US09978726
申请日：2001-10-18
申请人： Takuya Saze , Hirotaka Tamura , Takaya Chiba , Kohtaroh Gotoh , Hideki Ishida
发明人： Takuya Saze , Hirotaka Tamura , Takaya Chiba , Kohtaroh Gotoh , Hideki Ishida
IPC分类号： H04L25/00 , H03L7/06
CPC分类号： G11C7/1087 , G11C7/1078 , G11C7/222 , H03L7/0812 , H03L7/091 , H04L7/033 , H04L7/0337
摘要： A clock recovery circuit has a boundary detection/discrimination circuit to detect and discriminate a boundary in an input signal in accordance with a first signal. The clock recovery circuit performs clock recovery by controlling the timing of the first signal in accordance with the detected boundary, wherein boundary detection timing in the boundary detection/discrimination circuit is varied by controlling the first signal.

7. 发明授权

US06931344B2 Test circuit and semiconductor integrated circuit effectively carrying out verification of connection of nodes 有权
标题翻译：测试电路和半导体集成电路有效地执行节点连接的验证
公开(公告)号：US06931344B2
公开(公告)日：2005-08-16
申请号：US10082055
申请日：2002-02-26
申请人： Kohtaroh Gotoh , Koji Aoyagi , Kazuhiro Terashima , Shigeru Nishio
发明人： Kohtaroh Gotoh , Koji Aoyagi , Kazuhiro Terashima , Shigeru Nishio
IPC分类号： G01R31/28 , G01F19/00 , G01R31/317 , G01R31/3185 , H01L21/822 , H01L27/04
CPC分类号： G01R31/31713 , G01R31/318572
摘要： A test circuit is incorporated in a device having an output circuit for outputting a signal, and the test circuit carries out a verification of a connection of nodes of the device. The test circuit has a test data generating circuit and a test output buffer connected in parallel with output nodes of the output circuit. The test data generating circuit generates test data for carrying out a verification of a connection of the output nodes, and the test output buffer receives test data from the test data generating circuit and outputs the test data to the output nodes. Similarly, a test circuit is incorporated in a device having an input circuit for inputting a signal, and the test circuit carries out a verification of a connection of nodes of the device. The test circuit has a test data generating circuit and a test input buffer connected in parallel with input nodes of the input circuit. The test data generating circuit generates test data for carrying out a verification of a connection of the input nodes, and the test input buffer receives test data from the test data generating circuit and inputs the test data to the input nodes.
摘要翻译：测试电路被并入具有用于输出信号的输出电路的设备中，并且测试电路执行设备节点的连接的验证。测试电路具有与输出电路的输出节点并联连接的测试数据产生电路和测试输出缓冲器。测试数据产生电路产生用于执行输出节点的连接的验证的测试数据，并且测试输出缓冲器从测试数据产生电路接收测试数据，并将测试数据输出到输出节点。类似地，测试电路被并入具有用于输入信号的输入电路的设备中，并且测试电路执行设备节点的连接的验证。测试电路具有与输入电路的输入节点并联连接的测试数据产生电路和测试输入缓冲器。测试数据产生电路产生用于执行输入节点的连接的验证的测试数据，并且测试输入缓冲器从测试数据生成电路接收测试数据，并将测试数据输入到输入节点。

8. 发明授权

US06247138B1 Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system 失效
公开(公告)号：US06247138B1
公开(公告)日：2001-06-12
申请号：US09093056
申请日：1998-06-08
申请人： Hirotaka Tamura , Hisakatsu Araki , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
发明人： Hirotaka Tamura , Hisakatsu Araki , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
IPC分类号： G06F104
CPC分类号： H04L7/0337 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03K2005/00052 , H04L7/0025
摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

9. 发明授权

US5703819A Sense amplifier driving circuit 失效
标题翻译：感应放大器驱动电路
公开(公告)号：US5703819A
公开(公告)日：1997-12-30
申请号：US819509
申请日：1997-03-17
申请人： Kohtaroh Gotoh
发明人： Kohtaroh Gotoh
IPC分类号： G11C11/409 , G11C7/06 , G11C7/12 , H01L21/8238 , H01L27/092 , G11C13/00
CPC分类号： G11C7/06 , G11C7/065 , G11C7/12
摘要： A sense amplifier driving circuit includes bit-line connection transistors connected to link bit lines on the side of memory cells with bit lines on the side of a sense amplifier, a circuit for controlling ON/OFF operations of the bit-line connection transistors, and first and second capacitors coupled to respective sources of nMOS transistors and pMOS transistors constituting the sense amplifier. After a word line linked to the memory cell is turned ON to output cell data to the bit lines, the potentials at input gates of the bit-line connection transistors are lowered to a level permitting narrowing-down of a current flowing in the bit lines. Moreover, after the sense amplifier is activated, a difference voltage between the bit lines on the side of the sense amplifier is amplified sufficiently, and then a data read operation is completed. Thereafter, the bit-line connection transistors are turned ON to overdrive the sense amplifier through the first and second capacitors. This constitution contributes to a realization of a sense amplifier that can operate with a low power consumption and at high speed even at a low supply voltage.
摘要翻译：读出放大器驱动电路包括与读出放大器侧的位线连接到存储器单元侧的链路位线的位线连接晶体管，用于控制位线连接晶体管的导通/截止操作的电路，以及耦合到构成读出放大器的nMOS晶体管和pMOS晶体管的各个源的第一和第二电容器。在连接到存储器单元的字线被接通以将单元数据输出到位线之后，位线连接晶体管的输入栅极处的电位被降低到允许在位线中流动的电流变窄的水平。此外，在感测放大器被激活之后，读出放大器侧的位线之间的差分电压被充分放大，然后完成数据读取操作。此后，位线连接晶体管导通，通过第一和第二电容器对读出放大器过驱动。这种结构有助于实现即使在低电源电压下也能以低功耗和高速运行的读出放大器。

10. 发明授权

US07154918B2 Multiplexer circuit for converting parallel data into serial data at high speed and synchronized with a clock signal 有权
公开(公告)号：US07154918B2
公开(公告)日：2006-12-26
申请号：US10107052
申请日：2002-03-28
申请人： Hideki Takauchi , Kohtaroh Gotoh
发明人： Hideki Takauchi , Kohtaroh Gotoh
IPC分类号： H04J3/02
CPC分类号： H03K17/693 , H03M9/00
摘要： A multiplexer circuit, converting parallel data into serial data and synchronized with a clock signal, has a plurality of multiplexer cells that receive the parallel data. Each of the multiplexer cells has a first load, a plurality of first conductivity type transistors, and a level-changing circuit. The first conductivity type transistors are connected in series between a first power source line and a second power source line, and the level-changing circuit changes a connection node of adjacent first conductivity type transistors to a level of the first power source line.

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