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    • 3. 发明授权
    • AFSM circuit and method for low jitter PLL CMOS programmable divider
    • AFSM电路和低抖动PLL CMOS可编程分频器的方法
    • US07683679B2
    • 2010-03-23
    • US11985095
    • 2007-11-14
    • Hugo CheungJatinder Singh
    • Hugo CheungJatinder Singh
    • H03K21/00H03K23/00H03K25/00
    • H03K27/00H03K23/68
    • A frequency divider (10A) includes an asynchronous finite state machine (AFSM) configured as a counter (20) having an input coupled to an input clock signal (CLK) for producing information representative of a plurality of phase signals (F0,F1,F2,F3) each of which is a divided-down representation of the input clock signal (CLK) and each of which is phase-shifted by a predetermined amount with respect to another of the phase signals (F0,F1,F2,F3). Programmable circuitry (22) operates in response to both dynamic divide ratio information (DIV_RATIO) and the information representative of the plurality of phase signals (F0,F1,F2,F3) so as to generate an output clock signal (CLKOUT) that is divided down according to both the dynamic divide ratio information and the information representative of the plurality of phase signals (F0,F1,F2,F3).
    • 分频器(10A)包括被配置为计数器(20)的异步有限状态机(AFSM),其具有耦合到输入时钟信号(CLK)的输入,用于产生表示多个相位信号(F0,F1,F2 ,F3),其中的每一个是输入时钟信号(CLK)的分频表示,并且每个相对于另一个相位信号(F0,F1,F2,F3)相移一个预定量。 可编程电路(22)响应于动态分频比信息(DIV_RATIO)和表示多个相位信号(F0,F1,F2,F3)的信息而工作,以便产生分频的输出时钟信号(CLKOUT) 根据动态分频比信息和表示多个相位信号(F0,F1,F2,F3)的信息,下降。
    • 4. 发明授权
    • High speed dynamic frequency divider
    • 高速动态分频器
    • US07595668B2
    • 2009-09-29
    • US11680841
    • 2007-03-01
    • Tszshing Cheung
    • Tszshing Cheung
    • H03B19/00
    • H03K27/00H03K23/54
    • The frequency divider includes the buffer 30, the function selector 31 and the inverter 32. The output of the function selector 31 is input to the buffer 30. The output of the buffer 30 is fed back to the function selector 31 by two paths. One path includes the inverter 32 and the other does not. The function selector 31 selects one of the paths in synchronous with input clock CK. At one timing the output of the buffer 30 is flipped by the inverter 32. At the next timing the output of the buffer 30 is held the same by the function selector 31 selecting the path not including the inverter 32.
    • 分频器包括缓冲器30,功能选择器31和反相器32.功能选择器31的输出被输入到缓冲器30.缓冲器30的输出通过两条路径反馈到功能选择器31。 一个路径包括逆变器32,另一个路径不包括逆变器32。 功能选择器31选择与输入时钟CK同步的一个路径。 在一个定时,缓冲器30的输出被反相器32翻转。在下一个定时,由选择不包括逆变器32的路径的功能选择器31使缓冲器30的输出保持相同。