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1. 发明申请

US20110002374A1 RECEIVER CIRCUIT, METHOD OF ADJUSTING OFFSET, AND TRANSMISSION/RECEPTION SYSTEM 有权
标题翻译：接收电路，调整偏移的方法和传输/接收系统
公开(公告)号：US20110002374A1
公开(公告)日：2011-01-06
申请号：US12826420
申请日：2010-06-29
申请人： Masaya KIBUNE , Hirotaka Tamura
发明人： Masaya KIBUNE , Hirotaka Tamura
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H03K5/086 , H04L2025/03471 , H04L2025/03636 , H04L2025/03649 , H04L2025/03751
摘要： A receiver circuit includes: an equalization circuit that equalizes a first signal to obtain a second signal, and adjusts a characteristic of an equalization in accordance with an error between the second signal and a third signal; and a first offset adjustment circuit that adjusts an offset of the first signal in accordance with an error signal indicating the error.
摘要翻译：接收机电路包括：均衡电路，其对第一信号进行均衡以获得第二信号，并且根据第二信号和第三信号之间的误差调整均衡的特性; 以及第一偏移调整电路，其根据指示所述误差的误差信号来调整所述第一信号的偏移。

2. 发明授权

US07283601B2 Timing signal generating system and receiving circuit for transmitting signals at high speed with less circuitry 有权
标题翻译：定时信号发生系统和接收电路，用于以较少的电路高速传输信号
公开(公告)号：US07283601B2
公开(公告)日：2007-10-16
申请号：US10077875
申请日：2002-02-20
申请人： Hirotaka Tamura , Masaya Kibune
发明人： Hirotaka Tamura , Masaya Kibune
IPC分类号： H03D3/24
CPC分类号： G06F5/06 , G06F1/04 , H04L7/0012 , H04L7/005
摘要： A timing signal generating system has a clock signal generating circuit, a synchronizing circuit, a phase code recognizing circuit, and a calibration circuit. The clock signal generating circuit generates at least one first clock signal upon receipt of at least one reference clock signal by controlling an output phase thereof with a digital code signal. The synchronizing circuit hands over signals between a group of circuits operated by the first clock signal and an internal circuit operated by a second clock signal. The phase code recognizing circuit recognizes a phase code when the phases of the first clock signal and of the second clock signal are in a particular relationship. The calibration circuit calibrates a relationship between a value of the recognized phase code and a phase difference between the first and second clock signals. The synchronizing circuit is controlled by using phase code data calibrated by the calibration circuit.
摘要翻译：定时信号发生系统具有时钟信号发生电路，同步电路，相位代码识别电路和校准电路。时钟信号发生电路在接收到至少一个参考时钟信号时，通过用数字代码信号控制其输出相位来产生至少一个第一时钟信号。同步电路切换由第一时钟信号操作的一组电路与由第二时钟信号操作的内部电路之间的信号。当第一时钟信号和第二时钟信号的相位处于特定关系时，相位代码识别电路识别相位代码。校准电路校准识别的相位码的值与第一和第二时钟信号之间的相位差之间的关系。通过使用由校准电路校准的相位代码数据来控制同步电路。

3. 发明申请

US20050226355A1 Receiver circuit comprising equalizer 有权
标题翻译：接收器电路包括均衡器
公开(公告)号：US20050226355A1
公开(公告)日：2005-10-13
申请号：US11050175
申请日：2005-02-04
申请人： Masaya Kibune , Hirotaka Tamura
发明人： Masaya Kibune , Hirotaka Tamura
IPC分类号： H04L25/03 , H04B3/06 , H04B3/18 , H04L1/00
CPC分类号： H04L25/0328 , H04L25/03038
摘要： A receiver circuit has an equalizer that equalizes a received signal propagating through a transmission medium; a data detection circuit that detects an analog output signal of the equalizer at a data sample timing and outputs a digital signal; an intersymbol interference detection circuit that detects an intersymbol interference level from the analog output signal of the equalizer at the data sample timing and from the digital signal of the data detection circuit; and an equalization characteristic control unit that controls the characteristic of the equalizer to minimize the detected intersymbol interference level. The receiver circuit further has a data sample timing control unit in which the data sample timing is controlled to a sample timing at which the difference between the amplitude of the analog output waveform of the equalizer with respect to an impulse and the amplitude of an ideal impulse response waveform is minimal.
摘要翻译：接收机电路具有均衡器，其均衡通过传输介质传播的接收信号; 数据检测电路，在数据采样定时检测均衡器的模拟输出信号，并输出数字信号; 符号间干扰检测电路，在数据采样定时和数据检测电路的数字信号中，从均衡器的模拟输出信号中检测出符号间干扰电平; 以及均衡特性控制单元，其控制均衡器的特性以使检测到的符号间干扰电平最小化。接收器电路还具有数据采样定时控制单元，其中数据采样定时被控制到采样定时，在该采样定时处，均衡器的模拟输出波形的相对于脉冲的幅度与理想脉冲的振幅之差响应波形最小。

4. 发明申请

US20100019827A1 INTEGRATED CIRCUIT 有权
标题翻译：集成电路
公开(公告)号：US20100019827A1
公开(公告)日：2010-01-28
申请号：US12442459
申请日：2006-09-29
申请人： Hirotaka Tamura , Masaya Kibune
发明人： Hirotaka Tamura , Masaya Kibune
IPC分类号： H03K17/00
CPC分类号： H03K19/003 , H03K17/002 , H03K17/687
摘要： An integrated circuit includes a bypass signal path exchanging, between transceivers which are included in the integrated circuit, a signal transmitted/received between a transceiver of the transceivers and an internal logic circuit which processes data being input/output by transceiver with bypassing the internal logic circuit, a switch switching a pathway of the bypass signal path, and a switch changeover controller transferring a switch control signal that performs a changeover of the switch.
摘要翻译：集成电路包括在集成电路中包括的收发器之间的旁路信号路径交换在收发器的收发器之间发送/接收的信号和处理由收发器输入/输出的数据的内部逻辑电路，绕过内部逻辑开关切换旁路信号路径的路径，以及传送切换控制信号的切换控制信号的切换控制信号，切换控制信号进行切换。

5. 发明申请

US20090179674A1 Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission 审中-公开
标题翻译：相位合成电路和定时信号发生器电路，用于执行高速信号传输
公开(公告)号：US20090179674A1
公开(公告)日：2009-07-16
申请号：US12320698
申请日：2009-02-02
申请人： Hirotaka Tamura , Masaya Kibune
发明人： Hirotaka Tamura , Masaya Kibune
IPC分类号： H03K5/13 , H03L7/00
CPC分类号： G06G7/12 , H03K5/13 , H03K5/133 , H03K5/151 , H03K2005/00026 , H03K2005/0013 , H03K2005/00208 , H03L7/07 , H03L7/0812 , H03L7/0891 , H04L7/033
摘要： A phase-combining circuit for combining cyclic timing waveforms that have been phase-controlled by control signals based on three or more input signals of different phases, has a weight signal generating circuit and a weighting circuit. The weight signal generating circuit generates weights according to the control signals, and the weighting circuit gives the weights to the respective input signals, with a positive or negative polarity for each one signal.
摘要翻译：用于组合由基于三个或更多个不同相位的输入信号的控制信号进行相位控制的循环定时波形的相位合成电路具有加权信号产生电路和加权电路。权重信号发生电路根据控制信号产生加权，并且加权电路给每个输入信号赋予权重，每个信号具有正或负极性。

6. 发明授权

US07508892B2 Receiver circuit comprising equalizer 有权
标题翻译：接收器电路包括均衡器
公开(公告)号：US07508892B2
公开(公告)日：2009-03-24
申请号：US11050175
申请日：2005-02-04
申请人： Masaya Kibune , Hirotaka Tamura
发明人： Masaya Kibune , Hirotaka Tamura
IPC分类号： H03D1/06
CPC分类号： H04L25/0328 , H04L25/03038
摘要： A receiver circuit has an equalizer that equalizes a received signal propagating through a transmission medium; a data detection circuit that detects an analog output signal of the equalizer at a data sample timing and outputs a digital signal; an intersymbol interference detection circuit that detects an intersymbol interference level from the analog output signal of the equalizer at the data sample timing and from the digital signal of the data detection circuit; and an equalization characteristic control unit that controls the characteristic of the equalizer to minimize the detected intersymbol interference level. The receiver circuit further has a data sample timing control unit in which the data sample timing is controlled to a sample timing at which the difference between the amplitude of the analog output waveform of the equalizer with respect to an impulse and the amplitude of an ideal impulse response waveform is minimal.
摘要翻译：接收机电路具有均衡器，其均衡通过传输介质传播的接收信号; 数据检测电路，在数据采样定时检测均衡器的模拟输出信号，并输出数字信号; 符号间干扰检测电路，在数据采样定时和数据检测电路的数字信号中，从均衡器的模拟输出信号中检测出符号间干扰电平; 以及均衡特性控制单元，其控制均衡器的特性以使检测到的符号间干扰电平最小化。接收器电路还具有数据采样定时控制单元，其中数据采样定时被控制到采样定时，在该采样定时处，均衡器的模拟输出波形的相对于脉冲的幅度与理想脉冲的振幅之差响应波形最小。

7. 发明申请

US20050035789A1 Output circuit device for clock signal distribution in high-speed signal transmission 有权
公开(公告)号：US20050035789A1
公开(公告)日：2005-02-17
申请号：US10945965
申请日：2004-09-22
申请人： Hirotaka Tamura , Masaya Kibune
发明人： Hirotaka Tamura , Masaya Kibune
IPC分类号： H03K5/00 , H03F3/45 , H03K19/0175 , H03K5/22
CPC分类号： H03F3/4565 , H03F3/45192 , H03F3/45237 , H03F3/45659 , H03F2203/45418 , H03F2203/45446
摘要： An output circuit device has an output circuit connected between a first power supply line and a second power supply line via a control circuit having at least one isolating transistor. A control voltage held at a constant level is applied to a control electrode of the isolating transistor, and the control voltage is a voltage at a level that works to attenuate high-frequency components contained in a voltage supplied from the first or the second power supply line.

8. 发明授权

US08634454B2 Receiver circuit, method of adjusting offset, and transmission/reception system 有权
标题翻译：接收电路，调整偏移的方法以及发送/接收系统
公开(公告)号：US08634454B2
公开(公告)日：2014-01-21
申请号：US12826420
申请日：2010-06-29
申请人： Masaya Kibune , Hirotaka Tamura
发明人： Masaya Kibune , Hirotaka Tamura
IPC分类号： H03K5/159 , H04B1/10
CPC分类号： H04L25/03057 , H03K5/086 , H04L2025/03471 , H04L2025/03636 , H04L2025/03649 , H04L2025/03751
摘要： A receiver circuit includes: an equalization circuit that equalizes a first signal to obtain a second signal, and adjusts a characteristic of an equalization in accordance with an error between the second signal and a third signal; and a first offset adjustment circuit that adjusts an offset of the first signal in accordance with an error signal indicating the error.
摘要翻译：接收机电路包括：均衡电路，其对第一信号进行均衡以获得第二信号，并根据第二信号和第三信号之间的误差调整均衡的特性; 以及第一偏移调整电路，其根据指示所述误差的误差信号来调整所述第一信号的偏移。

9. 发明授权

US08319542B2 Integrated circuit including bypass signal path 有权
标题翻译：集成电路包括旁路信号路径
公开(公告)号：US08319542B2
公开(公告)日：2012-11-27
申请号：US12442459
申请日：2006-09-29
申请人： Hirotaka Tamura , Masaya Kibune
发明人： Hirotaka Tamura , Masaya Kibune
IPC分类号： H03K17/00
CPC分类号： H03K19/003 , H03K17/002 , H03K17/687
摘要： An integrated circuit includes a bypass signal path exchanging, between transceivers which are included in the integrated circuit, a signal transmitted/received between a transceiver of the transceivers and an internal logic circuit which processes data being input/output by transceiver with bypassing the internal logic circuit, a switch switching a pathway of the bypass signal path, and a switch changeover controller transferring a switch control signal that performs a changeover of the switch.
摘要翻译：集成电路包括在集成电路中包括的收发器之间的旁路信号路径交换在收发器的收发器之间发送/接收的信号和处理由收发器输入/输出的数据的内部逻辑电路，绕过内部逻辑开关切换旁路信号路径的路径，以及传送切换控制信号的切换控制信号的切换控制信号，切换控制信号进行切换。

10. 发明授权

US08238504B2 Clock generation circuit and system 失效
标题翻译：时钟发生电路和系统
公开(公告)号：US08238504B2
公开(公告)日：2012-08-07
申请号：US12633558
申请日：2009-12-08
申请人： Yasumoto Tomita , Masaya Kibune , Hirotaka Tamura
发明人： Yasumoto Tomita , Masaya Kibune , Hirotaka Tamura
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04L7/033 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/091 , H04L7/007 , H04L7/043
摘要： A clock generation circuit includes: a first determination circuit that detects an input signal at a first phase position based on first frequency signal; a second determination circuit that detects the input signal at a second phase position based on second frequency signal; a phase detector that compares output of the first determination circuit and output of the second determination circuit; a first summing circuit which sums comparison result and first control signal; a second summing circuit which sums comparison result and second control signal; a first voltage controlled oscillation circuit which receives output of the first summing circuit and outputs the first frequency signal; a second voltage controlled oscillation circuit which received output of the second summing circuit and outputs the second frequency signal; and a phase adjustment circuit which generates first control signal and second control signal based on first frequency signal and second frequency signal.
摘要翻译：时钟发生电路包括：第一确定电路，其基于第一频率信号检测第一相位位置处的输入信号; 第二确定电路，其基于第二频率信号来检测第二相位位置处的输入信号; 相位检测器，比较第一确定电路的输出和第二确定电路的输出; 第一求和电路，其将比较结果和第一控制信号相加; 第二加法电路，其将比较结果和第二控制信号相加; 第一压控振荡电路，接收第一求和电路的输出并输出第一频率信号; 接收第二加法电路的输出并输出第二频率信号的第二压控振荡电路; 以及基于第一频率信号和第二频率信号产生第一控制信号和第二控制信号的相位调整电路。

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