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1. 发明申请

US20050021929A1 Micro controller for processing compressed codes 失效
标题翻译：用于处理压缩码的微控制器
公开(公告)号：US20050021929A1
公开(公告)日：2005-01-27
申请号：US10611315
申请日：2003-06-30
申请人： Hiromichi Yamada , Yuichi Abe , Yasuhiro Nakatsuka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Yuichi Abe , Yasuhiro Nakatsuka , Takanaga Yamazaki
IPC分类号： G06F9/32 , G06F5/00 , G06F9/30 , G06F9/318 , G06F12/04
CPC分类号： G06F9/30145 , G06F9/30178
摘要： The invention provides a code compression technology that is favorable for a micro controller or other embedded system, and for compressed codes, resulting from conversion of program codes into variable length codes, and grouped program codes, address conversion information for specifying the start address of each group and compressed code type information for specifying the code length of each compressed code contained in a group are stored in a memory, and by enabling a corresponding compressed code address to be calculated from a code address output by a CPU, code compression that is favorable for a micro controller or other embedded system is realized.
摘要翻译：本发明提供了一种有利于微控制器或其他嵌入式系统的代码压缩技术，以及由程序代码转换为可变长度代码而导致的压缩代码，以及分组程序代码，用于指定每个的开始地址的地址转换信息用于指定包含在组中的每个压缩代码的代码长度的组和压缩代码类型信息被存储在存储器中，并且通过使得能够根据CPU输出的代码地址来计算相应的压缩代码地址，这是有利的代码压缩实现微控制器或其他嵌入式系统。

2. 发明授权

US07676651B2 Micro controller for decompressing and compressing variable length codes via a compressed code dictionary 失效
标题翻译：微控制器，用于通过压缩代码字典对可变长度代码进行解压缩和压缩
公开(公告)号：US07676651B2
公开(公告)日：2010-03-09
申请号：US10611315
申请日：2003-06-30
申请人： Hiromichi Yamada , Yuichi Abe , Yasuhiro Nakatsuka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Yuichi Abe , Yasuhiro Nakatsuka , Takanaga Yamazaki
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30178
摘要： The invention provides a code compression technology that is favorable for a micro controller or other embedded system, and for compressed codes, resulting from conversion of program codes into variable length codes, and grouped program codes, address conversion information for specifying the start address of each group and compressed code type information for specifying the code length of each compressed code contained in a group are stored in a memory, and by enabling a corresponding compressed code address to be calculated from a code address output by a CPU, code compression that is favorable for a micro controller or other embedded system is realized.
摘要翻译：本发明提供了一种有利于微控制器或其他嵌入式系统的代码压缩技术，以及由程序代码转换为可变长度代码而导致的压缩代码，以及分组程序代码，用于指定每个的开始地址的地址转换信息用于指定包含在组中的每个压缩代码的代码长度的组和压缩代码类型信息被存储在存储器中，并且通过使得能够根据CPU输出的代码地址来计算相应的压缩代码地址，这是有利的代码压缩实现微控制器或其他嵌入式系统。

3. 发明授权

US06915413B2 Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein 失效
公开(公告)号：US06915413B2
公开(公告)日：2005-07-05
申请号：US10101480
申请日：2002-03-20
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F7/36 , G06F9/45 , G06F17/30
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

4. 发明授权

US06986029B2 Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein 失效
公开(公告)号：US06986029B2
公开(公告)日：2006-01-10
申请号：US10201249
申请日：2002-07-24
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
IPC分类号： G06F7/06 , G06F15/76
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

5. 发明申请

US20050198471A1 Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein 审中-公开
标题翻译：用于读出压缩指令代码的微控制器和用于压缩指令代码并存储在其中的程序存储器
公开(公告)号：US20050198471A1
公开(公告)日：2005-09-08
申请号：US11117509
申请日：2005-04-29
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.
摘要翻译：微控制器包括用于存储出现在程序中的指令代码的字典存储器和用于存储从程序中包括的每个指令代码转换的压缩代码的压缩代码存储器。每个压缩代码的字长足够长以识别程序中包含的所有指令代码。每个压缩代码具有指示存储相关联的指令代码的字典存储器中的地址的值。微控制器响应于指定代码读取请求，其指定压缩代码的地址以读取存储在压缩代码存储器中的指定地址中的压缩代码，并且随后读取存储在由压缩代码存储器指示的地址中的指令代码字典内存中的压缩代码。

6. 发明授权

US07290124B2 Data processor employing register banks with overflow protection to enhance interrupt processing and task switching 有权
标题翻译：数据处理器采用具有溢出保护功能的寄存器组来增强中断处理和任务切换
公开(公告)号：US07290124B2
公开(公告)日：2007-10-30
申请号：US10690643
申请日：2003-10-23
申请人： Yasuo Sugure , Tomomi Ishikura , Kazuya Hirayanagi , Takeshi Kataoka , Seiji Takeuchi , Hiromichi Yamada , Takanaga Yamazaki
发明人： Yasuo Sugure , Tomomi Ishikura , Kazuya Hirayanagi , Takeshi Kataoka , Seiji Takeuchi , Hiromichi Yamada , Takanaga Yamazaki
IPC分类号： G06F9/48
CPC分类号： G06F9/30043 , G06F9/3012 , G06F9/30123
摘要： The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.
摘要翻译：本发明防止数据处理器由于多个寄存器组的溢出而不期望的操作停止。状态寄存器包括用于指示多个寄存器组的溢出的溢出标志。当数据已被保存到寄存器组的所有存储体的状态中发生中断异常时，允许接受的中断异常使用寄存器组，中央处理单元将寄存器组的数据保存到堆栈区域，反映溢出标志中的溢出状态。当溢出标志指示溢出状态时，如果从寄存器组到寄存器组的数据恢复被定向，则中央处理单元将数据从堆栈区恢复到寄存器组。

7. 发明授权

US5680637A Computer having a parallel operating capability 失效
标题翻译：具有并行操作能力的计算机
公开(公告)号：US5680637A
公开(公告)日：1997-10-21
申请号：US599856
申请日：1996-02-13
申请人： Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Hiromichi Yamada , Hideo Maejima
发明人： Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Hiromichi Yamada , Hideo Maejima
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/30189 , G06F9/30043 , G06F9/30079 , G06F9/38 , G06F9/383 , G06F9/3836 , G06F9/3853 , G06F9/3885
摘要： A RISC processor is arranged to reduce a code size, make the hardware less complicated, execute a plurality of operations for one machine cycle, and enhance the performance. The processor is capable of executing N instruction each having a short word length for indicating a single operation or an instruction having a long word length for indicating M (N
摘要翻译： RISC处理器被设置为减少代码大小，使硬件更不复杂，对一个机器周期执行多个操作，并提高性能。处理器能够执行每个具有用于指示单个操作的短字长的N指令或具有用于指示M（N

8. 发明授权

US08639905B2 Microcontroller and electronic control unit 有权
标题翻译：微控制器和电子控制单元
公开(公告)号：US08639905B2
公开(公告)日：2014-01-28
申请号：US13614313
申请日：2012-09-13
申请人： Hiromichi Yamada , Yuichi Ishiguro , Nobuyasu Kanekawa
发明人： Hiromichi Yamada , Yuichi Ishiguro , Nobuyasu Kanekawa
IPC分类号： G06F12/02
CPC分类号： G06F11/1641 , G06F11/1683
摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.
摘要翻译：其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入两次，并且第一次和第二次的写入数据被相互整理。

9. 发明授权

US07260657B2 Serial data transferring apparatus 有权
标题翻译：串行数据传输设备
公开(公告)号：US07260657B2
公开(公告)日：2007-08-21
申请号：US10491285
申请日：2001-10-02
申请人： Masahiro Matsumoto , Fumio Murabayashi , Hiromichi Yamada , Keiji Hanzawa , Hiroyasu Sukesako
发明人： Masahiro Matsumoto , Fumio Murabayashi , Hiromichi Yamada , Keiji Hanzawa , Hiroyasu Sukesako
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： H04L7/10 , H04J3/24 , H04J7/00 , H04L7/046 , H04L7/06
摘要： A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer. A serial data transferring apparatus is realized which can simplify the structure of the slave unit, cut the total cost, and reduce noise.
摘要翻译：主单元向从单元发送启动信号。当从主单元接收到起始信号时，从单元向主单元发送同步字段，该同步字段是指示从单元能够执行传送和接收操作的传送时钟的数据串（脉冲信号）。主单元根据从从单元发送的同步字段指示的传送时钟向从属单元发送命令数据。响应于从主单元发送的命令数据，从单元根据由同步字段指示的传送时钟向主单元发送响应数据。因此，在采用本发明的串行数据传送装置的通信系统中，主单元建立用于数据传送的同步，而从单元没有建立用于数据传送的同步的负担。实现了串行数据传送装置，其可以简化从单元的结构，降低总成本并降低噪声。

10. 发明申请

US20070180317A1 ERROR CORRECTION METHOD 有权
标题翻译：错误校正方法
公开(公告)号：US20070180317A1
公开(公告)日：2007-08-02
申请号：US11623441
申请日：2007-01-16
申请人： Teppei HIROTSU , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
发明人： Teppei HIROTSU , Hiromichi Yamada , Teruaki Sakata , Kesami Hagiwara
IPC分类号： G06F11/00
CPC分类号： G06F11/1407
摘要： This method is an error correction method such that, when an error is detected in a CPU with pipeline struct, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.
摘要翻译：该方法是一种错误校正方法，使得当在具有流水线结构的CPU中检测到错误时，通过延迟的寄存器文件来恢复寄存器文件的内容，该延迟寄存器文件保持在之前正确执行的[指令N]的执行完成状态该错误和执行作为[指令N]的下一条指令的[指令N + 1]的指令的回滚控制。该方法收集CPU内存在的任意Flip-Flops的奇偶校验结果，并检测出错误。结果，寄存器文件的内容被恢复到可能由错误导致故障的指令范围之前的指令执行完成状态，并且可以从可能由错误发生故障的指令范围的开始滚转指令。

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