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1. 发明授权

US09323595B2 Microcontroller, control device and determination method 有权
标题翻译：微控制器，控制装置及测定方法
公开(公告)号：US09323595B2
公开(公告)日：2016-04-26
申请号：US13555123
申请日：2012-07-21
申请人： Hiromichi Yamada , Teruaki Sakata , Nobuyasu Kanekawa , Yuichi Ishiguro , Takashi Yasumasu , Kazuyoshi Fukuda , Kesami Hagiwara
发明人： Hiromichi Yamada , Teruaki Sakata , Nobuyasu Kanekawa , Yuichi Ishiguro , Takashi Yasumasu , Kazuyoshi Fukuda , Kesami Hagiwara
IPC分类号： G05B19/29 , G06F11/07
CPC分类号： G06F11/0754 , G06F11/0739 , G06F13/00 , Y02D10/14
摘要： A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.
摘要翻译：微控制器包括中央处理单元，根据由中央处理单元设置的PWM信号的生成条件产生PWM信号的PWM信号生成单元，以及在其中输入生成的PWM信号并检测脉冲周期的诊断单元以及基于输入信号的脉冲宽度，并且确定检测到的脉冲周期和脉冲宽度是否与脉冲周期和对应于生成条件的脉冲宽度一致。

2. 发明申请

US20140032860A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR OPERATING SAME 有权
标题翻译：半导体集成电路及其工作方法
公开(公告)号：US20140032860A1
公开(公告)日：2014-01-30
申请号：US14110786
申请日：2011-04-21
申请人： Hiromichi Yamada , Nobuyasu Kanekawa , Teruaki Sakata , Kesami Hagiwara , Yuichi Ishiguro
发明人： Hiromichi Yamada , Nobuyasu Kanekawa , Teruaki Sakata , Kesami Hagiwara , Yuichi Ishiguro
IPC分类号： G06F12/02
CPC分类号： G06F12/02 , G06F11/1641 , G06F11/167 , G06F11/1687 , G06F2201/845
摘要： First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.
摘要翻译：从功能模块（2）输出的要写入的第一数据被提供给内置存储器（3）和第一缓冲存储器（11），以及从功能模块（2）输出的要写入的第二数据）被提供给内置存储器（3）和第二缓冲存储器（12）。第一和第二FIFO存储器（13,14）从从第一和第二缓冲存储器（11,12）顺次输出的多个第一和第二输出数据项中选择并存储具有预定数量的输出的数据项，以及不要选择其他数据项。比较器（15）将由第一和第二FIFO存储器（13,14）输出的具有预定数量的输出的数据项彼此进行比较。

3. 发明申请

US20130013881A1 MICROCONTROLLER AND ELECTRONIC CONTROL UNIT 有权
标题翻译：微控制器和电子控制单元
公开(公告)号：US20130013881A1
公开(公告)日：2013-01-10
申请号：US13614313
申请日：2012-09-13
申请人： Hiromichi YAMADA , Yuichi ISHIGURO , Nobuyasu KANEKAWA
发明人： Hiromichi YAMADA , Yuichi ISHIGURO , Nobuyasu KANEKAWA
IPC分类号： G06F12/00
CPC分类号： G06F11/1641 , G06F11/1683
摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.
摘要翻译：其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入两次，并且第一次和第二次的写入数据被相互整理。

4. 发明申请

US20110283033A1 COMPUTER SYSTEM 有权
标题翻译：电脑系统
公开(公告)号：US20110283033A1
公开(公告)日：2011-11-17
申请号：US13106788
申请日：2011-05-12
申请人： Hiromichi YAMADA , Kotaro Shimamura , Nobuyasu Kanekawa , Yuichi Ishiguro
发明人： Hiromichi YAMADA , Kotaro Shimamura , Nobuyasu Kanekawa , Yuichi Ishiguro
IPC分类号： G06F13/24 , G06F13/26
CPC分类号： G06F13/24 , G06F11/1641 , G06F2201/845
摘要： A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.
摘要翻译：提供了一种缩短CPU的待机时间并提高从性能模式（并行操作）切换到安全模式（主/检测器操作）时的CPU处理效率的计算机系统。在一个计算机系统中，包括：至少两个CPU; 用于中断CPU的可编程中断控制器; 以及比较器，用于相互比较CPU的输出，分别由CPU执行相互不同的处理的性能模式之间进行切换，以提高CPU的性能和执行相同处理的安全模式，并将比较器的结果进行比较检测失败可以进行; 可以为每个中断因子设置要中断的CPU; 并且可以针对每个中断因子来设置执行性能模式还是执行安全模式。

5. 发明授权

US09367438B2 Semiconductor integrated circuit and method for operating same 有权
标题翻译：半导体集成电路及其操作方法
公开(公告)号：US09367438B2
公开(公告)日：2016-06-14
申请号：US14110786
申请日：2011-04-21
申请人： Hiromichi Yamada , Nobuyasu Kanekawa , Teruaki Sakata , Kesami Hagiwara , Yuichi Ishiguro
发明人： Hiromichi Yamada , Nobuyasu Kanekawa , Teruaki Sakata , Kesami Hagiwara , Yuichi Ishiguro
IPC分类号： G06F12/02 , G06F11/16
CPC分类号： G06F12/02 , G06F11/1641 , G06F11/167 , G06F11/1687 , G06F2201/845
摘要： First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.
摘要翻译：从功能模块（2）输出的要写入的第一数据被提供给内置存储器（3）和第一缓冲存储器（11），以及从功能模块（2）输出的要写入的第二数据）被提供给内置存储器（3）和第二缓冲存储器（12）。第一和第二FIFO存储器（13,14）从从第一和第二缓冲存储器（11,12）顺次输出的多个第一和第二输出数据项中选择并存储具有预定数量的输出的数据项，以及不要选择其他数据项。比较器（15）将由第一和第二FIFO存储器（13,14）输出的具有预定数量的输出的数据项彼此进行比较。

6. 发明申请

US20130020978A1 MICROCONTROLLER, CONTROL DEVICE AND DETERMINATION METHOD 有权
标题翻译：微控制器，控制装置和测定方法
公开(公告)号：US20130020978A1
公开(公告)日：2013-01-24
申请号：US13555123
申请日：2012-07-21
申请人： Hiromichi YAMADA , Teruaki Sakata , Nobuyasu Kanekawa , Yuichi Ishiguro , Takashi Yasumasu , Kazuyoshi Fukuda , Kesami Hagiwara
发明人： Hiromichi YAMADA , Teruaki Sakata , Nobuyasu Kanekawa , Yuichi Ishiguro , Takashi Yasumasu , Kazuyoshi Fukuda , Kesami Hagiwara
IPC分类号： H02P7/29 , G05B9/02
CPC分类号： G06F11/0754 , G06F11/0739 , G06F13/00 , Y02D10/14
摘要： A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.
摘要翻译：微控制器包括中央处理单元，根据由中央处理单元设置的PWM信号的生成条件产生PWM信号的PWM信号生成单元，以及在其中输入生成的PWM信号并检测脉冲周期的诊断单元以及基于输入信号的脉冲宽度，并且确定检测到的脉冲周期和脉冲宽度是否与脉冲周期和对应于生成条件的脉冲宽度一致。

7. 发明申请

US20100217943A1 MICROCONTROLLER AND ELECTRONIC CONTROL UNIT 有权
标题翻译：微控制器和电子控制单元
公开(公告)号：US20100217943A1
公开(公告)日：2010-08-26
申请号：US12706938
申请日：2010-02-17
申请人： Hiromichi YAMADA , Yuichi ISHIGURO , Nobuyasu KANEKAWA
发明人： Hiromichi YAMADA , Yuichi ISHIGURO , Nobuyasu KANEKAWA
IPC分类号： G06F12/00
CPC分类号： G06F11/1641 , G06F11/1683
摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.
摘要翻译：其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入两次，并且第一次和第二次的写入数据被相互整理。

8. 发明授权

US08589612B2 Computer system including an interrupt controller 有权
标题翻译：计算机系统包括一个中断控制器
公开(公告)号：US08589612B2
公开(公告)日：2013-11-19
申请号：US13106788
申请日：2011-05-12
申请人： Hiromichi Yamada , Kotaro Shimamura , Nobuyasu Kanekawa , Yuichi Ishiguro
发明人： Hiromichi Yamada , Kotaro Shimamura , Nobuyasu Kanekawa , Yuichi Ishiguro
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F11/1641 , G06F2201/845
摘要： A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.
摘要翻译：提供一种缩短CPU的待机时间并提高从性能模式（并行操作）切换到安全模式（主/检测器操作）时的CPU处理效率的计算机系统。在一个计算机系统中，包括：至少两个CPU; 用于中断CPU的可编程中断控制器; 以及比较器，用于相互比较CPU的输出，分别由CPU执行相互不同的处理的性能模式之间进行切换，以提高CPU的性能和执行相同处理的安全模式，并将比较器的结果进行比较检测失败可以进行; 可以为每个中断因子设置要中断的CPU; 并且可以针对每个中断因子来设置执行性能模式还是执行安全模式。

9. 发明授权

US08433955B2 Multi-core microcontroller having comparator for checking processing result 有权
标题翻译：具有用于检查处理结果的比较器的多核微控制器
公开(公告)号：US08433955B2
公开(公告)日：2013-04-30
申请号：US12610422
申请日：2009-11-02
申请人： Hiromichi Yamada , Kotaro Shimamura , Kesami Hagiwara , Yoshikazu Kiyoshige , Yuichi Ishiguro
发明人： Hiromichi Yamada , Kotaro Shimamura , Kesami Hagiwara , Yoshikazu Kiyoshige , Yuichi Ishiguro
IPC分类号： G06F11/00
CPC分类号： G06F11/1608 , G06F11/004 , G06F11/1641 , G06F11/1687 , G06F2201/83 , G06F2201/845
摘要： A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.
摘要翻译：一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。即使当多个CPU异步执行相同的处理时，获得相同处理结果的定时也是不同的，因此压缩机进行压缩，因此可以容易地将它们的处理结果进行比较。此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。

10. 发明授权

US08291188B2 Microcontroller and electronic control unit 有权
标题翻译：微控制器和电子控制单元
公开(公告)号：US08291188B2
公开(公告)日：2012-10-16
申请号：US12706938
申请日：2010-02-17
申请人： Hiromichi Yamada , Yuichi Ishiguro , Nobuyasu Kanekawa
发明人： Hiromichi Yamada , Yuichi Ishiguro , Nobuyasu Kanekawa
IPC分类号： G06F12/12
CPC分类号： G06F11/1641 , G06F11/1683
摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.
摘要翻译：其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入两次，并且第一次和第二次的写入数据被相互整理。

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