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1. 发明授权

US09037448B2 Computer system, program, and method for assigning computational resource to be used in simulation 有权
标题翻译：用于分配计算资源的计算机系统，程序和方法用于仿真
公开(公告)号：US09037448B2
公开(公告)日：2015-05-19
申请号：US13387243
申请日：2010-07-16
申请人： Yasuhiro Ito , Yasuo Sugure , Shigeru Oho , Hideaki Kurata
发明人： Yasuhiro Ito , Yasuo Sugure , Shigeru Oho , Hideaki Kurata
IPC分类号： G06F9/44 , G06F11/36 , G06F9/50
CPC分类号： G06F11/3664 , G06F9/5055
摘要： The cost necessary for introducing and maintaining a development environment that includes multiple simulators is suppressed, and a sharing of designing information is promoted, to make parameter adjustment of simulators easy. Provided is a service that unifies development environment on a computer provided with: a working computer system that can guarantee that there is no leaking of designing files; a user behavior monitoring system that collects utilization history of simulators or software, for each of the users, and selects development process of each of the users from the collected information; and a dynamic computational-resource distribution system that can conduct an automatic optimization of a complex simulation configuration, from information collected by the aforementioned user behavior monitoring system.
摘要翻译：引入和维护包含多个模拟器的开发环境所需的成本被抑制，并且提高了设计信息的共享，从而使模拟器的参数调整变得容易。提供了一种将计算机上的开发环境统一起来的服务，它具有：可以保证设计文件不泄漏的工作计算机系统; 用户行为监控系统，用于为每个用户收集模拟器或软件的利用历史，并从收集的信息中选择每个用户的开发过程; 以及动态计算资源分配系统，可以从上述用户行为监控系统收集的信息中进行复杂模拟配置的自动优化。

2. 发明授权

US07987075B2 Apparatus and method to develop multi-core microcomputer-based systems 有权
标题翻译：开发基于多核微机的系统的设备和方法
公开(公告)号：US07987075B2
公开(公告)日：2011-07-26
申请号：US12164178
申请日：2008-06-30
申请人： Yasuo Sugure , Donald J. McCune , Sujit Phatak , George Saikalis
发明人： Yasuo Sugure , Donald J. McCune , Sujit Phatak , George Saikalis
IPC分类号： G06F17/50 , G06F3/00
CPC分类号： G06F17/5022 , G06F2217/68
摘要： A method and apparatus for developing multicore microcomputer-based systems. A dual core controller model having at least one parameter is simulated and, similarly, a plant model having at least one parameter and controlled by the controller model is also simulated. The user interface then has access to the parameters of the controller model and plant model and optionally suspends execution of the controller model and plant model in response to a trigger event. The user interface determines the status of the various controller model parameters for both cores and/or plant model parameters at the time of the trigger without altering the controller model parameters or the plant model parameters. The core parameters for both cores are displayed on a display device.
摘要翻译：一种用于开发基于多核微机的系统的方法和装置。模拟具有至少一个参数的双核控制器模型，并且类似地，还模拟具有至少一个参数并由控制器模型控制的工厂模型。然后，用户界面可以访问控制器模型和工厂模型的参数，并且可选地中止响应于触发事件的控制器模型和工厂模型的执行。用户界面在触发时确定两个核心和/或工厂模型参数的各种控制器模型参数的状态，而不改变控制器模型参数或工厂模型参数。两个核心的核心参数显示在显示设备上。

3. 发明申请

US20090327944A1 APPARATUS AND METHOD TO DEVELOP MULTI-CORE MICROCOMPUTER-BASED SYSTEMS 有权
标题翻译：用于开发基于多核微型计算机的系统的设备和方法
公开(公告)号：US20090327944A1
公开(公告)日：2009-12-31
申请号：US12164178
申请日：2008-06-30
申请人： Yasuo Sugure , Donald J. McCune , Sujit Phatak , George Saikalis
发明人： Yasuo Sugure , Donald J. McCune , Sujit Phatak , George Saikalis
IPC分类号： G06F3/048 , G06G7/48
CPC分类号： G06F17/5022 , G06F2217/68
摘要： A method and apparatus for developing multicore microcomputer-based systems. A dual core controller model having at least one parameter is simulated and, similarly, a plant model having at least one parameter and controlled by the controller model is also simulated. The user interface then has access to the parameters of the controller model and plant model and optionally suspends execution of the controller model and plant model in response to a trigger event. The user interface determines the status of the various controller model parameters for both cores and/or plant model parameters at the time of the trigger without altering the controller model parameters or the plant model parameters. The core parameters for both cores are displayed on a display device.
摘要翻译：一种用于开发基于多核微机的系统的方法和装置。模拟具有至少一个参数的双核控制器模型，并且类似地，还模拟具有至少一个参数并由控制器模型控制的工厂模型。然后，用户界面可以访问控制器模型和工厂模型的参数，并且可选地中止响应于触发事件的控制器模型和工厂模型的执行。用户界面在触发时确定两个核心和/或工厂模型参数的各种控制器模型参数的状态，而不改变控制器模型参数或工厂模型参数。两个核心的核心参数显示在显示设备上。

4. 发明申请

US20080046697A1 DATA PROCESSOR 审中-公开
标题翻译：数据处理器
公开(公告)号：US20080046697A1
公开(公告)日：2008-02-21
申请号：US11868471
申请日：2007-10-06
申请人： Yasuo SUGURE , Tomomi ISHIKURA , Kazuya HIRAYANAGI , Takeshi KATAOKA , Seiji TAKEUCHI , Hiromichi YAMADA , Takanaga YAMAZAKI
发明人： Yasuo SUGURE , Tomomi ISHIKURA , Kazuya HIRAYANAGI , Takeshi KATAOKA , Seiji TAKEUCHI , Hiromichi YAMADA , Takanaga YAMAZAKI
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/3012 , G06F9/30123
摘要： The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.
摘要翻译：本发明防止数据处理器由于多个寄存器组的溢出而不期望的操作停止。状态寄存器包括用于指示多个寄存器组的溢出的溢出标志。当数据已被保存到寄存器组的所有存储体的状态中发生中断异常时，允许接受的中断异常使用寄存器组，中央处理单元将寄存器组的数据保存到堆栈区域，反映溢出标志中的溢出状态。当溢出标志指示溢出状态时，如果从寄存器组到寄存器组的数据恢复被定向，则中央处理单元将数据从堆栈区恢复到寄存器组。

5. 发明授权

US09606902B2 Malfunction influence evaluation system and evaluation method using a propagation flag 有权
公开(公告)号：US09606902B2
公开(公告)日：2017-03-28
申请号：US14404844
申请日：2012-07-03
申请人： Akihiko Hyodo , Yasuo Sugure , Yasuhiro Ito , Tetsuya Yamada
发明人： Akihiko Hyodo , Yasuo Sugure , Yasuhiro Ito , Tetsuya Yamada
IPC分类号： G06F11/36 , G05B19/042 , G05B23/02
CPC分类号： G06F11/3688 , G05B19/0428 , G05B23/0213 , G06F11/3636 , G06F11/3644 , G06F11/3664
摘要： Provided is a malfunction influence evaluation system comprising a controller simulator that simulates the operation of a controller, an input apparatus that provides input data to the controller simulator, a simulation manager that exercises integrated management of the operation of the input apparatus and the controller simulator, and a database wherein malfunction information and simulation conditions to be referred to by the simulation manager is stored. The controller simulator retains a control program for the controller and an analysis unit, and the analysis unit has a propagation flag tracking function wherein propagation flags are assigned to a variable within the control program, bits of the variable are set by inputting a prescribed value thereto as a malfunction input value, the bits are propagated each time the variable is involved in a calculation within the control program, the states of propagation of the bits are tracked, and the result thereof is output.

6. 发明申请

US20120123764A1 Computer System, Program, and Method for Assigning Computational Resource to be Used in Simulation 有权
标题翻译：计算机系统，程序和分配用于仿真的计算资源的方法
公开(公告)号：US20120123764A1
公开(公告)日：2012-05-17
申请号：US13387243
申请日：2010-07-16
申请人： Yasuhiro Ito , Yasuo Sugure , Shigeru Oho , Hideaki Kurata
发明人： Yasuhiro Ito , Yasuo Sugure , Shigeru Oho , Hideaki Kurata
IPC分类号： G06F17/50
CPC分类号： G06F11/3664 , G06F9/5055
摘要： The cost necessary for introducing and maintaining a development environment that includes multiple simulators is suppressed, and a sharing of designing information is promoted, to make parameter adjustment of simulators easy. Provided is a service that unifies development environment on a computer provided with: a working computer system that can guarantee that there is no leaking of designing files; a user behavior monitoring system that collects utilization history of simulators or software, for each of the users, and selects development process of each of the users from the collected information; and a dynamic computational-resource distribution system that can conduct an automatic optimization of a complex simulation configuration, from information collected by the aforementioned user behavior monitoring system.
摘要翻译：引入和维护包含多个模拟器的开发环境所需的成本被抑制，并且提高了设计信息的共享，从而使模拟器的参数调整变得容易。提供了一种将计算机上的开发环境统一起来的服务，它具有：可以保证设计文件不泄漏的工作计算机系统; 用户行为监控系统，用于为每个用户收集模拟器或软件的利用历史，并从收集的信息中选择每个用户的开发过程; 以及动态计算资源分配系统，可以从上述用户行为监控系统收集的信息中进行复杂模拟配置的自动优化。

7. 发明授权

US07290124B2 Data processor employing register banks with overflow protection to enhance interrupt processing and task switching 有权
标题翻译：数据处理器采用具有溢出保护功能的寄存器组来增强中断处理和任务切换
公开(公告)号：US07290124B2
公开(公告)日：2007-10-30
申请号：US10690643
申请日：2003-10-23
申请人： Yasuo Sugure , Tomomi Ishikura , Kazuya Hirayanagi , Takeshi Kataoka , Seiji Takeuchi , Hiromichi Yamada , Takanaga Yamazaki
发明人： Yasuo Sugure , Tomomi Ishikura , Kazuya Hirayanagi , Takeshi Kataoka , Seiji Takeuchi , Hiromichi Yamada , Takanaga Yamazaki
IPC分类号： G06F9/48
CPC分类号： G06F9/30043 , G06F9/3012 , G06F9/30123
摘要： The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.
摘要翻译：本发明防止数据处理器由于多个寄存器组的溢出而不期望的操作停止。状态寄存器包括用于指示多个寄存器组的溢出的溢出标志。当数据已被保存到寄存器组的所有存储体的状态中发生中断异常时，允许接受的中断异常使用寄存器组，中央处理单元将寄存器组的数据保存到堆栈区域，反映溢出标志中的溢出状态。当溢出标志指示溢出状态时，如果从寄存器组到寄存器组的数据恢复被定向，则中央处理单元将数据从堆栈区恢复到寄存器组。

8. 发明申请

US20150121148A1 MALFUNCTION INFLUENCE EVALUATION SYSTEM AND EVALUATION METHOD 有权
标题翻译：功能影响评估系统和评估方法
公开(公告)号：US20150121148A1
公开(公告)日：2015-04-30
申请号：US14404844
申请日：2012-07-03
申请人： Akihiko Hyodo , Yasuo Sugure , Yasuhiro Ito , Tetsuya Yamada
发明人： Akihiko Hyodo , Yasuo Sugure , Yasuhiro Ito , Tetsuya Yamada
IPC分类号： G06F11/36
CPC分类号： G06F11/3688 , G05B19/0428 , G05B23/0213 , G06F11/3636 , G06F11/3644 , G06F11/3664
摘要： Provided is a malfunction influence evaluation system comprising a controller simulator that simulates the operation of a controller, an input apparatus that provides input data to the controller simulator, a simulation manager that exercises integrated management of the operation of the input apparatus and the controller simulator, and a database wherein malfunction information and simulation conditions to be referred to by the simulation manager is stored. The controller simulator retains a control program for the controller and an analysis unit, and the analysis unit has a propagation flag tracking function wherein propagation flags are assigned to a variable within the control program, bits of the variable are set by inputting a prescribed value thereto as a malfunction input value, the bits are propagated each time the variable is involved in a calculation within the control program, the states of propagation of the bits are tracked, and the result thereof is output.
摘要翻译：提供了一种故障影响评估系统，其包括模拟控制器的操作的控制器模拟器，向控制器模拟器提供输入数据的输入装置，对输入装置和控制器模拟器的操作进行综合管理的模拟管理器，以及存储由模拟管理器参考的故障信息和模拟条件的数据库。控制器模拟器保持控制器和分析单元的控制程序，并且分析单元具有传播标志跟踪功能，其中传播标志被分配给控制程序内的变量，通过向其输入规定的值来设置变量的位作为故障输入值，每当该变量涉及控制程序内的计算时，这些比特被传播，跟踪该比特的传播状态并输出其结果。

9. 发明授权

US07398378B2 Allocating lower priority interrupt for processing to slave processor via master processor currently processing higher priority interrupt through special interrupt among processors 有权
标题翻译：通过主处理器为处理器分配低优先级中断，当前通过处理器之间的特殊中断处理较高优先级的中断
公开(公告)号：US07398378B2
公开(公告)日：2008-07-08
申请号：US11453902
申请日：2006-06-16
申请人： Yasuo Sugure , Kenta Morishima
发明人： Yasuo Sugure , Kenta Morishima
IPC分类号： G06F9/44
CPC分类号： G06F9/4812 , G06F13/24
摘要： In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP) provided with an operating system (OS), a slave processor (SP), an interrupt controller (INTC), and an interrupt among processors control register (IPCR) are connected to one another. The INTC has an interrupt among processors request control logic for master processor (IPRCLMP), an interrupt among processors request control logic for slave processor (IPRCLSP), and an interrupt among processors disable judgment logic for master processor (IPDJLMP). When the SP finishes the interrupt process after the MP has executed an interrupt process higher in priority and the SP has executed an interrupt process lower in priority, the IPDJLMP determines whether or not other interrupt requests have arrived and outputs an interrupt request from the SP to the MP according to the determination result.
摘要翻译：在具有主从配置的多处理器系统中，在处理器之间有效地分配和处理中断以提高实时性能。具有操作系统（OS），从属处理器（SP），中断控制器（INTC）和处理器控制寄存器（IPCR）中的中断的主处理器（MP）彼此连接。 INTC在处理器之间有一个中断请求主处理器（IPRCLMP）的控制逻辑，处理器之间的中断请求从属处理器（IPRCLSP）的控制逻辑，并且处理器之间的中断禁止主处理器（IPDJLMP）的判断逻辑。当MP完成中断处理后，MP执行优先级更高的中断处理，并且SP执行优先级较低的中断处理，IPDJLMP确定其他中断请求是否已到达，并将SP中断请求输出到 MP根据确定结果。

10. 发明申请

US20060294348A1 Multi-processor system 有权
标题翻译：多处理器系统
公开(公告)号：US20060294348A1
公开(公告)日：2006-12-28
申请号：US11453902
申请日：2006-06-16
申请人： Yasuo Sugure , Kenta Morishima
发明人： Yasuo Sugure , Kenta Morishima
IPC分类号： G06F9/44
CPC分类号： G06F9/4812 , G06F13/24
摘要： In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP) provided with an operating system (OS), a slave processor (SP), an interrupt controller (INTC), and an interrupt among processors control register (IPCR) are connected to one another. The INTC has an interrupt among processors request control logic for master processor (IPRCLMP), an interrupt among processors request control logic for slave processor (IPRCLSP), and an interrupt among processors disable judgment logic for master processor (IPDJLMP). When the SP finishes the interrupt process after the MP has executed an interrupt process higher in priority and the SP has executed an interrupt process lower in priority, the IPDJLMP determines whether or not other interrupt requests have arrived and outputs an interrupt request from the SP to the MP according to the determination result.
摘要翻译：在具有主从配置的多处理器系统中，在处理器之间有效地分配和处理中断以提高实时性能。具有操作系统（OS），从属处理器（SP），中断控制器（INTC）和处理器控制寄存器（IPCR）中的中断的主处理器（MP）彼此连接。 INTC在处理器之间有一个中断请求主处理器（IPRCLMP）的控制逻辑，处理器之间的中断请求从属处理器（IPRCLSP）的控制逻辑，并且处理器之间的中断禁止主处理器（IPDJLMP）的判断逻辑。当MP完成中断处理后，MP执行优先级更高的中断处理，并且SP执行优先级较低的中断处理，IPDJLMP确定其他中断请求是否已到达，并将SP中断请求输出到 MP根据确定结果。

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