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1. 发明授权

US07414874B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07414874B2
公开(公告)日：2008-08-19
申请号：US11588328
申请日：2006-10-27
申请人： Hiroki Fujisawa , Isamu Fujii , Yuko Watanabe
发明人： Hiroki Fujisawa , Isamu Fujii , Yuko Watanabe
IPC分类号： G11C5/02
CPC分类号： H01L27/105 , G11C5/025 , G11C11/4097
摘要： Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.
摘要翻译：公开了一种半导体存储器件，包括存储单元阵列块和沿着第一方向布置有存储单元阵列块的电路区域。电路区域包括沿第一方向布置有第一区域的第一区域和第二区域。第一区域设置有在垂直于第一方向的第二方向上排列的第一电路和第二电路。第二区域设置有沿第二方向排列的多个第三电路。

2. 发明申请

US20070096156A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070096156A1
公开(公告)日：2007-05-03
申请号：US11588328
申请日：2006-10-27
申请人： Hiroki Fujisawa , Isamu Fujii , Yuko Watanabe
发明人： Hiroki Fujisawa , Isamu Fujii , Yuko Watanabe
IPC分类号： H01L27/10
CPC分类号： H01L27/105 , G11C5/025 , G11C11/4097
摘要： Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.
摘要翻译：公开了一种半导体存储器件，包括存储单元阵列块和沿着第一方向布置有存储单元阵列块的电路区域。电路区域包括沿第一方向布置有第一区域的第一区域和第二区域。第一区域设置有在垂直于第一方向的第二方向上排列的第一电路和第二电路。第二区域设置有沿第二方向排列的多个第三电路。

3. 发明授权

US06954398B2 Semiconductor memory device including subword drivers 失效
标题翻译：半导体存储器件包括子字驱动器
公开(公告)号：US06954398B2
公开(公告)日：2005-10-11
申请号：US10633710
申请日：2003-08-05
申请人： Kouichiro Ninomiya , Isamu Fujii , Hiroki Fujisawa
发明人： Kouichiro Ninomiya , Isamu Fujii , Hiroki Fujisawa
IPC分类号： G11C11/407 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/408 , G11C8/00
CPC分类号： G11C8/08 , G11C8/14 , G11C11/4085
摘要： A semiconductor memory device is capable of performing a faster operation by reducing a load applied to a subword selection line or driving a subword driver provided for each memory mat. In a drive method of subword drivers that are actuated in response to subword selection signals supplied through subword selection lines, the subword selection lines are branched according to the number of memory mats. Each subword selection signal has a polarity to a branching position and an inverted polarity from each branching position to each subword driver. The inverted subword selection signal together with a main word signal are calculated to operation in each subword driver and output as a subword drive signal. The plurality of subword drivers share an inverter circuit for inverting the main word signals so as to permit a simplified circuit configuration.
摘要翻译：半导体存储器件能够通过减小施加到子选择线的负载或驱动为每个存储器垫提供的子字驱动器来执行更快的操作。在响应于通过子选择线提供的子字选择信号被致动的子字驱动器的驱动方法中，子字选择线根据存储器数的数量被分支。每个子字选择信号具有分支位置的极性和从每个分支位置到每个子字驱动器的反相极性。计算出反相子字选择信号与主字信号一起在每个子字驱动器中的操作，并作为子字驱动信号输出。多个子字驱动器共享用于反转主字信号的逆变器电路，以便允许简化的电路配置。

4. 发明授权

US08633758B2 Semiconductor device having boosting circuit 失效
标题翻译：具有升压电路的半导体装置
公开(公告)号：US08633758B2
公开(公告)日：2014-01-21
申请号：US13064237
申请日：2011-03-11
申请人： Hiroki Fujisawa , Shuichi Kubouchi , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Shuichi Kubouchi , Hitoshi Tanaka
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/46 , G11C5/145 , H02M1/15 , H02M3/07 , H02M2001/0045
摘要： A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.
摘要翻译：一种半导体器件包括：升压电路，其根据外部电源电压升压升压范围内的内部电源电压;将外部电源电压与规定的基准电压进行比较的外部电压电平比较电路;以及可变电阻器电路包括连接到升压电路的输出端子的可变电阻器。可变电阻电路基于外部电压电平比较电路的比较结果来控制可变电阻器的电阻值。

5. 发明授权

US08630129B2 Semiconductor device having plural banks 失效
标题翻译：具有多个堤的半导体装置
公开(公告)号：US08630129B2
公开(公告)日：2014-01-14
申请号：US13304062
申请日：2011-11-23
申请人： Hiroki Fujisawa , Yuuji Motoyama
发明人： Hiroki Fujisawa , Yuuji Motoyama
IPC分类号： G11C7/10
CPC分类号： G11C11/4087 , G11C11/4096 , G11C11/4097
摘要： A semiconductor device is provided with a control circuit generating a plurality of first control signals indicating timings at which column switches conduct at the time of reading and a plurality of second control signals indicating timings at which the column switches conduct at the time of writing. The control circuit activates the plurality of first control signals such that timing at which the data read from each of memory cell arrays arrives at a FIFO circuit after reception of a read instruction from outside is the same in each bank and activates the plurality of second control signals such that the column switches match a timing at which write data input from outside to a first data input/output terminal arrives at the corresponding column switch.
摘要翻译：半导体器件设置有控制电路，该控制电路产生多个第一控制信号，该第一控制信号指示列开关在读取时导通的定时;以及多个第二控制信号，其指示列开关在写入时进行的定时。控制电路激活多个第一控制信号，使得在从外部接收到读指令之后从每个存储单元阵列读取的数据到达FIFO电路的定时在每个存储体中相同，并激活多个第二控制信号使得列开关匹配从外部输入到第一数据输入/输出端的写入数据到达对应的列开关的定时。

6. 发明授权

US08553489B2 Semiconductor device having point-shift type FIFO circuit 有权
标题翻译：具有点移型FIFO电路的半导体器件
公开(公告)号：US08553489B2
公开(公告)日：2013-10-08
申请号：US13317601
申请日：2011-10-24
申请人： Hiroki Fujisawa , Yuuji Motoyama
发明人： Hiroki Fujisawa , Yuuji Motoyama
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C8/18 , G11C11/408
摘要： For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal.
摘要翻译：例如，半导体器件包括锁存电路，其输入节点连接到输入选择电路，其输出节点连接到输出选择电路; 以及控制电路，其控制输入选择电路和输出选择电路。控制电路包括用于产生输入指针信号的移位寄存器和产生输出指针信号的二进制计数器。输入选择电路基于输入指针信号的值选择一个锁存电路。输出选择电路根据输出指针信号的值选择一个锁存电路。因此，可以防止在输入选择电路中发生危险，并且可以减少发送输出指针信号的信号线的数量。

7. 发明授权

US08427856B2 Semiconductor device having bit lines and local I/O lines 失效
标题翻译：具有位线和本地I / O线的半导体器件
公开(公告)号：US08427856B2
公开(公告)日：2013-04-23
申请号：US13246458
申请日：2011-09-27
申请人： Shingo Mitsubori , Hiroki Fujisawa
发明人： Shingo Mitsubori , Hiroki Fujisawa
IPC分类号： G11C5/06
CPC分类号： G11C29/025 , G11C2029/1204
摘要： The present invention efficiently decides line failure and contact failure in a semiconductor device. The semiconductor device has a plurality of bit line groups in which connection with local I/O lines is controlled by the same column selection signal line. A failure detecting circuit compares a first data group read from a first bit line group and a second data group read from a second bit line group to detect whether or not connection failure (contact failure) with the column selection signal line occurs in one of the first and second bit line groups.
摘要翻译：本发明有效地确定半导体器件中的线路故障和接触故障。半导体器件具有多个位线组，其中与本地I / O线的连接由相同的列选择信号线控制。故障检测电路比较从第一位线组读取的第一数据组和从第二位线组读取的第二数据组，以检测与列选择信号线的连接故障（接触故障）是否发生在第一和第二位线组。

8. 发明授权

US08422326B2 Semiconductor device having sense amplifier 有权
标题翻译：具有读出放大器的半导体器件
公开(公告)号：US08422326B2
公开(公告)日：2013-04-16
申请号：US13304040
申请日：2011-11-23
申请人： Hiroki Fujisawa , Ryuuji Takishita
发明人： Hiroki Fujisawa , Ryuuji Takishita
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C7/065
摘要： For example, four driver transistors are arranged in wells so as to adjoin both sides of each of two element isolation regions. Two pairs of cross-coupled sense transistors are arranged in the wells at positions farther from the element isolation regions than the driver transistors are. Such an arrangement provides more than a certain distance between the sense transistors and the respective corresponding element isolation regions. This reduces the effect of a phenomenon that threshold of a transistor varies according to a distance from an element isolation region. As a result, it is possible to exactly match the characteristics of each pair of cross-coupled transistors.
摘要翻译：例如，四个驱动晶体管布置在阱中，以便邻接两个元件隔离区域中的每一个的两侧。两个交叉耦合的检测晶体管布置在阱中，比驱动晶体管更远离元件隔离区的位置。这种布置在感测晶体管和相应的对应元件隔离区域之间提供超过一定距离。这降低了晶体管的阈值根据与元件隔离区域的距离而变化的现象的影响。结果，可以精确地匹配每对交叉耦合晶体管的特性。

9. 发明授权

US08274843B2 Semiconductor device having nonvolatile memory element and data processing system including the same 有权
公开(公告)号：US08274843B2
公开(公告)日：2012-09-25
申请号：US12695784
申请日：2010-01-28
申请人： Yoshio Mizukane , Hiroki Fujisawa
发明人： Yoshio Mizukane , Hiroki Fujisawa
IPC分类号： G11C7/10 , G11C17/16 , G11C7/00
CPC分类号： G11C11/4072 , G11C7/1045 , G11C7/1066 , G11C7/20
摘要： A semiconductor device includes a fuse element, a read-out circuit that reads out a memory content of the fuse element in response to a first internal reset signal that is activated in response to transition of an external reset signal, and a latch circuit that holds therein the memory content read out by the read-out circuit and is reset by a second internal reset signal that is activated based on an activation period of the external reset signal. With this configuration, even when the activation period of the external reset signal is long, the time for which a current flows through the fuse element can be shortened, thereby making it possible to reduce a current consumption at the time of a reset operation.

10. 发明申请

US20120120753A1 Semiconductor device having point-shift type FIFO circuit 有权
标题翻译：具有点移型FIFO电路的半导体器件
公开(公告)号：US20120120753A1
公开(公告)日：2012-05-17
申请号：US13317601
申请日：2011-10-24
申请人： Hiroki Fujisawa , Yuuji Motoyama
发明人： Hiroki Fujisawa , Yuuji Motoyama
IPC分类号： G11C8/06 , G11C8/10
CPC分类号： G11C11/4076 , G11C8/18 , G11C11/408
摘要： For example, a semiconductor device includes latch circuits, whose input nodes are connected to an input selection circuit and whose output nodes are connected to an output selection circuit; and a control circuit, which controls the input selection circuit and the output selection circuit. The control circuit includes a shift register to generate an input pointer signal and a binary counter to generate an output pointer signal. The input selection circuit selects one of the latch circuits on the basis of a value of the input pointer signal. The output selection circuit selects one of the latch circuits on the basis of a value of the output pointer signal. Therefore, it is possible to prevent a hazard from occurring in the input selection circuit, as well as to reduce the number of signal lines that transmit the output pointer signal.
摘要翻译：例如，半导体器件包括锁存电路，其输入节点连接到输入选择电路，其输出节点连接到输出选择电路; 以及控制电路，其控制输入选择电路和输出选择电路。控制电路包括用于产生输入指针信号的移位寄存器和产生输出指针信号的二进制计数器。输入选择电路基于输入指针信号的值选择一个锁存电路。输出选择电路根据输出指针信号的值选择一个锁存电路。因此，可以防止在输入选择电路中发生危险，并且可以减少发送输出指针信号的信号线的数量。

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