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1. 发明申请

US20110221513A1 Semiconductor device having boosting circuit 失效
标题翻译：具有升压电路的半导体装置
公开(公告)号：US20110221513A1
公开(公告)日：2011-09-15
申请号：US13064237
申请日：2011-03-11
申请人： Hiroki Fujisawa , Shuichi Kubouchi , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Shuichi Kubouchi , Hitoshi Tanaka
IPC分类号： G05F1/10
CPC分类号： G05F1/46 , G11C5/145 , H02M1/15 , H02M3/07 , H02M2001/0045
摘要： A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.
摘要翻译：一种半导体器件包括：升压电路，其根据外部电源电压升压升压范围内的内部电源电压;将外部电源电压与规定的基准电压进行比较的外部电压电平比较电路;以及可变电阻器电路包括连接到升压电路的输出端子的可变电阻器。可变电阻电路基于外部电压电平比较电路的比较结果来控制可变电阻器的电阻值。

2. 发明授权

US08633758B2 Semiconductor device having boosting circuit 失效
标题翻译：具有升压电路的半导体装置
公开(公告)号：US08633758B2
公开(公告)日：2014-01-21
申请号：US13064237
申请日：2011-03-11
申请人： Hiroki Fujisawa , Shuichi Kubouchi , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Shuichi Kubouchi , Hitoshi Tanaka
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F1/46 , G11C5/145 , H02M1/15 , H02M3/07 , H02M2001/0045
摘要： A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.
摘要翻译：一种半导体器件包括：升压电路，其根据外部电源电压升压升压范围内的内部电源电压;将外部电源电压与规定的基准电压进行比较的外部电压电平比较电路;以及可变电阻器电路包括连接到升压电路的输出端子的可变电阻器。可变电阻电路基于外部电压电平比较电路的比较结果来控制可变电阻器的电阻值。

3. 发明授权

US06765844B2 Semiconductor memory device having a hierarchical I/O structure 有权
公开(公告)号：US06765844B2
公开(公告)日：2004-07-20
申请号：US10658396
申请日：2003-09-10
申请人： Hiroki Fujisawa , Shuichi Kubouchi , Koichiro Ninomiya
发明人： Hiroki Fujisawa , Shuichi Kubouchi , Koichiro Ninomiya
IPC分类号： G11C800
CPC分类号： G11C7/10 , G11C5/025 , G11C5/063 , G11C8/12 , G11C8/14 , G11C11/4093
摘要： Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.

4. 发明授权

US07085192B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07085192B2
公开(公告)日：2006-08-01
申请号：US11004796
申请日：2004-12-07
申请人： Hiroki Fujisawa , Shuichi Kubouchi
发明人： Hiroki Fujisawa , Shuichi Kubouchi
IPC分类号： G11C8/00
CPC分类号： G11C7/109 , G11C7/1066 , G11C7/1078 , G11C7/22 , G11C11/4076 , G11C11/4082 , G11C11/4093
摘要： In a semiconductor integrated circuit device, a write command decoder decodes a write command and outputs decode pulses. A command counter circuit counts the decode pulses as the number of commands. A latch circuit latches the write aDDRess in response to a count output from the command counter circuit. A latency counter circuit counts a latency in response to the decode pulses. The semiconductor integrated circuit device further includes a circuit for turning on a column selection control signal when the count value of the latency counter circuit exceeds a predetermined latency value and a circuit for outputting the aDDRess latched by the latch circuit as a column aDDRess in response to the column selection control signal being turned on. The semiconductor integrated circuit device performs a write operation to the column aDDRess in response to the column selection control signal being turned on.
摘要翻译：在半导体集成电路装置中，写命令解码器对写命令进行解码并输出译码脉冲。命令计数器电路将解码脉冲计数为命令数。锁存电路根据命令计数器电路的计数输出锁存写入数据。延迟计数器电路响应于解码脉冲对等待时间进行计数。半导体集成电路装置还包括：当等待时间计数器电路的计数值超过预定等待时间值时，用于接通列选择控制信号的电路，以及用于响应于第二个锁存电路输出由锁存电路锁存的DDRess作为列dDessess的电路列选择控制信号被接通。半导体集成电路装置响应于列选择控制信号被导通而对列aDDRess执行写操作。

5. 发明授权

US06665203B2 Semiconductor memory device having a hierarchial I/O strucuture 有权
标题翻译：具有分层I / O结构的半导体存储器件
公开(公告)号：US06665203B2
公开(公告)日：2003-12-16
申请号：US09866623
申请日：2001-05-30
申请人： Hiroki Fujisawa , Shuichi Kubouchi , Koichiro Ninomiya
发明人： Hiroki Fujisawa , Shuichi Kubouchi , Koichiro Ninomiya
IPC分类号： G11C502
CPC分类号： G11C7/10 , G11C5/025 , G11C5/063 , G11C8/12 , G11C8/14 , G11C11/4093
摘要： Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.
摘要翻译：存储器阵列区域，每个存储器阵列区域包括沿着第一方向提供的多个位线，沿着与第一方向正交的第二方向设置的多个字线;以及多个存储器单元，其与多个位线并且多个字线分别以第一方向以多个形式相交并且相对于读出放大器区域交替设置。提供了通过位线连接的第一公共输入/输出线和与这种读出放大器区域相关联的第一选择电路。提供了通过多个第一公共输入/输出线连接的第二公共输入/输出线和对应于沿着第一方向设置的多个存储器阵列的第二选择电路。第二公共输入/输出线中的每一个被扩展以形成用于传送从每个存储单元读取的信号和写入其中的信号的信号传送通道。

6. 发明申请

US20110058402A1 Semiconductor device having nonvolatile memory elements 有权
标题翻译：具有非易失性存储元件的半导体器件
公开(公告)号：US20110058402A1
公开(公告)日：2011-03-10
申请号：US12923165
申请日：2010-09-07
申请人： Shuichi Kubouchi , Hiroki Fujisawa
发明人： Shuichi Kubouchi , Hiroki Fujisawa
IPC分类号： G11C17/16
CPC分类号： G11C17/18
摘要： A bit memory circuit of an antifuse element set includes two antifuse elements of which logical states are changed from an insulation state to a conductive state when a program voltage is applied. 1-bit data is represented by the logical states of the two antifuse elements. The two antifuse elements are collectively controlled by one decoder circuit. When writing data, the decoder circuit simultaneously performs insulation-breakdown on the two antifuse elements by simultaneously connecting the two antifuse elements to program voltage lines, respectively.
摘要翻译：反熔丝元件组的位存储电路包括两个反熔丝元件，当施加编程电压时，逻辑状态从绝缘状态变为导通状态。 1位数据由两个反熔丝元件的逻辑状态表示。两个反熔丝元件由一个解码器电路共同控制。当写入数据时，解码器电路通过同时将两个反熔丝元件连接到编程电压线来同时对两个反熔丝元件进行绝缘击穿。

7. 发明授权

US06934214B2 Semiconductor memory device having a hierarchical I/O structure 有权
标题翻译：具有分层I / O结构的半导体存储器件
公开(公告)号：US06934214B2
公开(公告)日：2005-08-23
申请号：US10875209
申请日：2004-06-25
申请人： Hiroki Fujisawa , Shuichi Kubouchi , Koichiro Ninomiya
发明人： Hiroki Fujisawa , Shuichi Kubouchi , Koichiro Ninomiya
IPC分类号： G11C11/409 , G11C5/02 , G11C5/06 , G11C7/10 , G11C8/02 , G11C8/12 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/4093 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C7/10 , G11C5/025 , G11C5/063 , G11C8/12 , G11C8/14 , G11C11/4093
摘要： Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.
摘要翻译：存储器阵列区域，每个存储器阵列区域包括沿着第一方向提供的多个位线，沿着与第一方向正交的第二方向设置的多个字线;以及多个存储器单元，其与多个位线并且多个字线分别以第一方向以多个形式相交并且相对于读出放大器区域交替设置。提供了通过位线连接的第一公共输入/输出线和与这种读出放大器区域相关联的第一选择电路。提供了通过多个第一公共输入/输出线连接的第二公共输入/输出线和对应于沿着第一方向设置的多个存储器阵列的第二选择电路。第二公共输入/输出线中的每一个被扩展以形成用于传送从每个存储单元读取的信号和写入其中的信号的信号传送通道。

8. 发明申请

US20050122795A1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20050122795A1
公开(公告)日：2005-06-09
申请号：US11004796
申请日：2004-12-07
申请人： Hiroki Fujisawa , Shuichi Kubouchi
发明人： Hiroki Fujisawa , Shuichi Kubouchi
IPC分类号： G11C11/407 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/408 , G11C7/00
CPC分类号： G11C7/109 , G11C7/1066 , G11C7/1078 , G11C7/22 , G11C11/4076 , G11C11/4082 , G11C11/4093
摘要： In a semiconductor integrated circuit device, a write command decoder decodes a write command and outputs decode pulses. A command counter circuit counts the decode pulses as the number of commands. A latch circuit latches the write aDDRess in response to a count output from the command counter circuit. A latency counter circuit counts a latency in response to the decode pulses. The semiconductor integrated circuit device further includes a circuit for turning on a column selection control signal when the count value of the latency counter circuit exceeds a predetermined latency value and a circuit for outputting the aDDRess latched by the latch circuit as a column aDDRess in response to the column selection control signal being turned on. The semiconductor integrated circuit device performs a write operation to the column aDDRess in response to the column selection control signal being turned on.
摘要翻译：在半导体集成电路装置中，写命令解码器对写命令进行解码并输出译码脉冲。命令计数器电路将解码脉冲计数为命令数。锁存电路根据命令计数器电路的计数输出锁存写入数据。延迟计数器电路响应于解码脉冲对等待时间进行计数。半导体集成电路装置还包括：当等待时间计数器电路的计数值超过预定等待时间值时，用于接通列选择控制信号的电路，以及用于响应于第二个锁存电路输出由锁存电路锁存的DDRess作为列dDessess的电路列选择控制信号被接通。半导体集成电路装置响应于列选择控制信号被导通而对列aDDRess执行写操作。

9. 发明授权

US07580321B2 Synchronous semiconductor memory device 有权
标题翻译：同步半导体存储器件
公开(公告)号：US07580321B2
公开(公告)日：2009-08-25
申请号：US12071198
申请日：2008-02-19
申请人： Hiroki Fujisawa , Shuichi Kubouchi , Koji Kuroki
发明人： Hiroki Fujisawa , Shuichi Kubouchi , Koji Kuroki
IPC分类号： G11C8/00
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222
摘要： A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.
摘要翻译：本发明的同步半导体存储器件具有：时钟发生器，用于通过对外部时钟进行分频来产生正相和反相时钟;命令解码器，用于解码外部指令并输出命令信号; 延迟设置装置，其能够在外部时钟的预定时钟周期的范围内选择性地设置偶数或奇数等待时间;等待时间计数器，其包括两个计数器电路，用于顺序地移动使用正向和反相位时钟捕获的命令信号并且能够响应于时钟周期的数量切换信号路径;以及第一和第二控制装置，其通过形成适当的信号路径来控制等于偶数或奇数等待时间的时钟周期的计数。

10. 发明申请

US20070091714A1 Synchronous semiconductor memory device 有权
标题翻译：同步半导体存储器件
公开(公告)号：US20070091714A1
公开(公告)日：2007-04-26
申请号：US11583980
申请日：2006-10-20
申请人： Hiroki Fujisawa , Shuichi Kubouchi , Koji Kuroki
发明人： Hiroki Fujisawa , Shuichi Kubouchi , Koji Kuroki
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222
摘要： A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.
摘要翻译：本发明的同步半导体存储器件具有：时钟发生器，用于通过对外部时钟进行分频来产生正相和反相时钟;命令解码器，用于解码外部指令并输出命令信号; 延迟设置装置，其能够在外部时钟的预定时钟周期的范围内选择性地设置偶数或奇数等待时间;等待时间计数器，其包括两个计数器电路，用于顺序地移动使用正向和反相位时钟捕获的命令信号并且能够响应于时钟周期的数量切换信号路径;以及第一和第二控制装置，其通过形成适当的信号路径来控制等于偶数或奇数等待时间的时钟周期的计数。

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