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    • 4. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US07085192B2
    • 2006-08-01
    • US11004796
    • 2004-12-07
    • Hiroki FujisawaShuichi Kubouchi
    • Hiroki FujisawaShuichi Kubouchi
    • G11C8/00
    • G11C7/109G11C7/1066G11C7/1078G11C7/22G11C11/4076G11C11/4082G11C11/4093
    • In a semiconductor integrated circuit device, a write command decoder decodes a write command and outputs decode pulses. A command counter circuit counts the decode pulses as the number of commands. A latch circuit latches the write aDDRess in response to a count output from the command counter circuit. A latency counter circuit counts a latency in response to the decode pulses. The semiconductor integrated circuit device further includes a circuit for turning on a column selection control signal when the count value of the latency counter circuit exceeds a predetermined latency value and a circuit for outputting the aDDRess latched by the latch circuit as a column aDDRess in response to the column selection control signal being turned on. The semiconductor integrated circuit device performs a write operation to the column aDDRess in response to the column selection control signal being turned on.
    • 在半导体集成电路装置中,写命令解码器对写命令进行解码并输出译码脉冲。 命令计数器电路将解码脉冲计数为命令数。 锁存电路根据命令计数器电路的计数输出锁存写入数据。 延迟计数器电路响应于解码脉冲对等待时间进行计数。 半导体集成电路装置还包括:当等待时间计数器电路的计数值超过预定等待时间值时,用于接通列选择控制信号的电路,以及用于响应于第二个锁存电路输出由锁存电路锁存的DDRess作为列dDessess的电路 列选择控制信号被接通。 半导体集成电路装置响应于列选择控制信号被导通而对列aDDRess执行写操作。
    • 5. 发明授权
    • Semiconductor memory device having a hierarchial I/O strucuture
    • 具有分层I / O结构的半导体存储器件
    • US06665203B2
    • 2003-12-16
    • US09866623
    • 2001-05-30
    • Hiroki FujisawaShuichi KubouchiKoichiro Ninomiya
    • Hiroki FujisawaShuichi KubouchiKoichiro Ninomiya
    • G11C502
    • G11C7/10G11C5/025G11C5/063G11C8/12G11C8/14G11C11/4093
    • Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.
    • 存储器阵列区域,每个存储器阵列区域包括沿着第一方向提供的多个位线,沿着与第一方向正交的第二方向设置的多个字线;以及多个存储器单元,其与多个位线 并且多个字线分别以第一方向以多个形式相交并且相对于读出放大器区域交替设置。 提供了通过位线连接的第一公共输入/输出线和与这种读出放大器区域相关联的第一选择电路。 提供了通过多个第一公共输入/输出线连接的第二公共输入/输出线和对应于沿着第一方向设置的多个存储器阵列的第二选择电路。 第二公共输入/输出线中的每一个被扩展以形成用于传送从每个存储单元读取的信号和写入其中的信号的信号传送通道。
    • 6. 发明授权
    • Synchronous semiconductor memory device
    • 同步半导体存储器件
    • US07580321B2
    • 2009-08-25
    • US12071198
    • 2008-02-19
    • Hiroki FujisawaShuichi KubouchiKoji Kuroki
    • Hiroki FujisawaShuichi KubouchiKoji Kuroki
    • G11C8/00
    • G11C11/4076G11C7/22G11C7/222
    • A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.
    • 本发明的同步半导体存储器件具有:时钟发生器,用于通过对外部时钟进行分频来产生正相和反相时钟;命令解码器,用于解码外部指令并输出命令信号; 延迟设置装置,其能够在外部时钟的预定时钟周期的范围内选择性地设置偶数或奇数等待时间;等待时间计数器,其包括两个计数器电路,用于顺序地移动使用正向和反相位时钟捕获的命令信号 并且能够响应于时钟周期的数量切换信号路径;以及第一和第二控制装置,其通过形成适当的信号路径来控制等于偶数或奇数等待时间的时钟周期的计数。
    • 7. 发明申请
    • Synchronous semiconductor memory device
    • 同步半导体存储器件
    • US20070091714A1
    • 2007-04-26
    • US11583980
    • 2006-10-20
    • Hiroki FujisawaShuichi KubouchiKoji Kuroki
    • Hiroki FujisawaShuichi KubouchiKoji Kuroki
    • G11C7/00
    • G11C11/4076G11C7/22G11C7/222
    • A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.
    • 本发明的同步半导体存储器件具有:时钟发生器,用于通过对外部时钟进行分频来产生正相和反相时钟;命令解码器,用于解码外部指令并输出命令信号; 延迟设置装置,其能够在外部时钟的预定时钟周期的范围内选择性地设置偶数或奇数等待时间;等待时间计数器,其包括两个计数器电路,用于顺序地移动使用正向和反相位时钟捕获的命令信号 并且能够响应于时钟周期的数量切换信号路径;以及第一和第二控制装置,其通过形成适当的信号路径来控制等于偶数或奇数等待时间的时钟周期的计数。
    • 9. 发明授权
    • Semiconductor memory device having a hierarchical I/O structure
    • 具有分层I / O结构的半导体存储器件
    • US06934214B2
    • 2005-08-23
    • US10875209
    • 2004-06-25
    • Hiroki FujisawaShuichi KubouchiKoichiro Ninomiya
    • Hiroki FujisawaShuichi KubouchiKoichiro Ninomiya
    • G11C11/409G11C5/02G11C5/06G11C7/10G11C8/02G11C8/12G11C8/14G11C11/401G11C11/407G11C11/4093H01L21/8242H01L27/108G11C8/00
    • G11C7/10G11C5/025G11C5/063G11C8/12G11C8/14G11C11/4093
    • Memory array areas, each including a plurality of bit lines provided along a first direction, a plurality of word lines provided along a second direction orthogonal to the first direction, and a plurality of memory cells provided in association with portions where the plurality of bit lines and the plurality of word-lines intersect, respectively, are provided in plural form in the first direction and are disposed alternately relative to sense amplifier areas. First common input/output lines connected through bit lines and first selection circuits associated with such sense amplifier areas are provided. Second common input/output lines connected through the plurality of first common input/output lines and second selection circuits corresponding to a plurality of memory arrays disposed along the first direction are provided. Each of the second common input/output lines is extended to form a signal transfer channel for transferring a signal read from each memory cell and a signal written therein.
    • 存储器阵列区域,每个存储器阵列区域包括沿着第一方向提供的多个位线,沿着与第一方向正交的第二方向设置的多个字线;以及多个存储器单元,其与多个位线 并且多个字线分别以第一方向以多个形式相交并且相对于读出放大器区域交替设置。 提供了通过位线连接的第一公共输入/输出线和与这种读出放大器区域相关联的第一选择电路。 提供了通过多个第一公共输入/输出线连接的第二公共输入/输出线和对应于沿着第一方向设置的多个存储器阵列的第二选择电路。 第二公共输入/输出线中的每一个被扩展以形成用于传送从每个存储单元读取的信号和写入其中的信号的信号传送通道。
    • 10. 发明申请
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US20050122795A1
    • 2005-06-09
    • US11004796
    • 2004-12-07
    • Hiroki FujisawaShuichi Kubouchi
    • Hiroki FujisawaShuichi Kubouchi
    • G11C11/407G11C7/10G11C7/22G11C11/4076G11C11/408G11C7/00
    • G11C7/109G11C7/1066G11C7/1078G11C7/22G11C11/4076G11C11/4082G11C11/4093
    • In a semiconductor integrated circuit device, a write command decoder decodes a write command and outputs decode pulses. A command counter circuit counts the decode pulses as the number of commands. A latch circuit latches the write aDDRess in response to a count output from the command counter circuit. A latency counter circuit counts a latency in response to the decode pulses. The semiconductor integrated circuit device further includes a circuit for turning on a column selection control signal when the count value of the latency counter circuit exceeds a predetermined latency value and a circuit for outputting the aDDRess latched by the latch circuit as a column aDDRess in response to the column selection control signal being turned on. The semiconductor integrated circuit device performs a write operation to the column aDDRess in response to the column selection control signal being turned on.
    • 在半导体集成电路装置中,写命令解码器对写命令进行解码并输出译码脉冲。 命令计数器电路将解码脉冲计数为命令数。 锁存电路根据命令计数器电路的计数输出锁存写入数据。 延迟计数器电路响应于解码脉冲对等待时间进行计数。 半导体集成电路装置还包括:当等待时间计数器电路的计数值超过预定等待时间值时,用于接通列选择控制信号的电路,以及用于响应于第二个锁存电路输出由锁存电路锁存的DDRess作为列dDessess的电路 列选择控制信号被接通。 半导体集成电路装置响应于列选择控制信号被导通而对列aDDRess执行写操作。