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1. 发明授权

US08427856B2 Semiconductor device having bit lines and local I/O lines 失效
标题翻译：具有位线和本地I / O线的半导体器件
公开(公告)号：US08427856B2
公开(公告)日：2013-04-23
申请号：US13246458
申请日：2011-09-27
申请人： Shingo Mitsubori , Hiroki Fujisawa
发明人： Shingo Mitsubori , Hiroki Fujisawa
IPC分类号： G11C5/06
CPC分类号： G11C29/025 , G11C2029/1204
摘要： The present invention efficiently decides line failure and contact failure in a semiconductor device. The semiconductor device has a plurality of bit line groups in which connection with local I/O lines is controlled by the same column selection signal line. A failure detecting circuit compares a first data group read from a first bit line group and a second data group read from a second bit line group to detect whether or not connection failure (contact failure) with the column selection signal line occurs in one of the first and second bit line groups.
摘要翻译：本发明有效地确定半导体器件中的线路故障和接触故障。半导体器件具有多个位线组，其中与本地I / O线的连接由相同的列选择信号线控制。故障检测电路比较从第一位线组读取的第一数据组和从第二位线组读取的第二数据组，以检测与列选择信号线的连接故障（接触故障）是否发生在第一和第二位线组。

2. 发明授权

US08164372B2 Semiconductor device having level shift circuit, control method thereof, and data processing system 有权
标题翻译：具有电平移位电路的半导体器件，其控制方法和数据处理系统
公开(公告)号：US08164372B2
公开(公告)日：2012-04-24
申请号：US12923071
申请日：2010-08-31
申请人： Shingo Mitsubori , Kazutaka Miyano
发明人： Shingo Mitsubori , Kazutaka Miyano
IPC分类号： H03L7/06 , G11C7/00
CPC分类号： H03L7/0814 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093
摘要： To include a first level shift circuit that converts a first internal clock signal having an amplitude value of a first voltage into a second internal clock signal having an amplitude value of a second voltage, a second level shift circuit that converts a first internal data signal having the amplitude value of the first voltage into a second internal data signal having the amplitude value of the second voltage, a clock dividing circuit that generates third and fourth internal clock signals, which are complementary signals, based on the second internal clock signal, and an output circuit that outputs external data signals continuously from a data output terminal in synchronization with the third and fourth internal clock signals based on the second internal data signal. According to the present invention, because a level shift of a signal is performed before it is input to the output circuit, there occurs no skew in output data.
摘要翻译：为了包括将具有第一电压的振幅值的第一内部时钟信号转换成具有第二电压的振幅值的第二内部时钟信号的第一电平移位电路，转换具有第二电平移位电路的第一内部数据信号，将第一电压的振幅值转换成具有第二电压的振幅值的第二内部数据信号，基于第二内部时钟信号产生作为互补信号的第三和第四内部时钟信号的时钟分频电路，以及输出电路，其基于第二内部数据信号与第三和第四内部时钟信号同步地从数据输出端子连续地输出外部数据信号。根据本发明，由于在输入到输出电路之前执行信号的电平偏移，所以在输出数据中不发生偏斜。

3. 发明申请

US20110062998A1 Semiconductor device having level shift circuit, control method thereof, and data processing system 有权
标题翻译：具有电平移位电路的半导体器件，其控制方法和数据处理系统
公开(公告)号：US20110062998A1
公开(公告)日：2011-03-17
申请号：US12923071
申请日：2010-08-31
申请人： Shingo Mitsubori , Kazutaka Miyano
发明人： Shingo Mitsubori , Kazutaka Miyano
IPC分类号： H03L7/00
CPC分类号： H03L7/0814 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093
摘要： To include a first level shift circuit that converts a first internal clock signal having an amplitude value of a first voltage into a second internal clock signal having an amplitude value of a second voltage, a second level shift circuit that converts a first internal data signal having the amplitude value of the first voltage into a second internal data signal having the amplitude value of the second voltage, a clock dividing circuit that generates third and fourth internal clock signals, which are complementary signals, based on the second internal clock signal, and an output circuit that outputs external data signals continuously from a data output terminal in synchronization with the third and fourth internal clock signals based on the second internal data signal. According to the present invention, because a level shift of a signal is performed before it is input to the output circuit, there occurs no skew in output data.
摘要翻译：为了包括将具有第一电压的振幅值的第一内部时钟信号转换成具有第二电压的振幅值的第二内部时钟信号的第一电平移位电路，转换具有第二电平移位电路的第一内部数据信号，将第一电压的振幅值转换成具有第二电压的振幅值的第二内部数据信号，基于第二内部时钟信号产生作为互补信号的第三和第四内部时钟信号的时钟分频电路，以及输出电路，其基于第二内部数据信号与第三和第四内部时钟信号同步地从数据输出端子连续地输出外部数据信号。根据本发明，由于在输入到输出电路之前执行信号的电平偏移，所以在输出数据中不发生偏斜。

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