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1. 发明授权

US06877039B2 Simplified pipeline writes over a network 有权
标题翻译：简化的流水线通过网络写入
公开(公告)号：US06877039B2
公开(公告)日：2005-04-05
申请号：US09842481
申请日：2001-04-25
申请人： Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie , Hirohide Sugahara
发明人： Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie , Hirohide Sugahara
IPC分类号： H04L12/40 , H04L12/28 , H04L29/06 , H04L29/08 , G06F15/16 , G06F13/36 , G08C25/02
CPC分类号： H04L29/06 , H04L69/324
摘要： A system and method are provided for efficiently writing data from one bus device to another bus device across a network. Data packets to be transmitted are ordered and assigned sequence numbers and expected sequence numbers. The expected sequence number of a data packet corresponds to the sequence number of the data packet immediately prior to the current data packet. When a data packet arrives at the receiving bus, its expected sequence number is compared against the sequence numbers of the previous data packets received. If the previously-received data packet bears the sequence number corresponding to the expected sequence number of the newly arrived data packet, the newly arrived data is stored, and an acknowledgement is sent. If a match cannot be found then a retry request message is sent.
摘要翻译：提供了一种系统和方法，用于通过网络有效地将数据从一个总线设备写入另一总线设备。要发送的数据包被排序并分配序列号和预期的序列号。数据分组的期望序列号对应于紧接当前数据分组之前的数据分组的序列号。当数据分组到达接收总线时，将其预期序列号与接收的先前数据分组的序列号进行比较。如果先前接收到的数据分组具有与新到达的数据分组的预期序列号相对应的序列号，则存储新到达的数据，并发送确认。如果无法找到匹配项，则发送重试请求消息。

2. 发明授权

US06684281B1 Fast delivery of interrupt message over network 有权
标题翻译：通过网络快速传递中断消息
公开(公告)号：US06684281B1
公开(公告)日：2004-01-27
申请号：US09705451
申请日：2000-11-02
申请人： Hirohide Sugahara , Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie
发明人： Hirohide Sugahara , Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A computer network system and a method for fast delivery of an interrupt message over a computer network enables a first processor coupled to the computer network to very quickly send an interrupt message to a second processor coupled to the computer network, by directly writing the interrupt message to a doorbell address range associated with the second processor in the PCI memory space of a first PCI bus to which the first processor is coupled. The doorbell address range is mapped to a doorbell space in the PCI memory space of a second PCI bus to which the second processor is coupled. The first PCI bus is coupled to the computer network through a first PCI network adaptor, which processes the write transaction and send it to the network. The second PCI bus is coupled to the computer network through a second PCI network adaptor, which receives the write transaction from the network and transforms the write transaction into an interrupt message to the second processor.
摘要翻译：计算机网络系统和用于通过计算机网络快速传递中断消息的方法使得耦合到计算机网络的第一处理器能够通过直接写入中断消息来非常快速地向耦合到计算机网络的第二处理器发送中断消息涉及与第一处理器耦合到的第一PCI总线的PCI存储器空间中与第二处理器相关联的门铃地址范围。门铃地址范围被映射到与第二处理器耦合到的第二PCI总线的PCI存储器空间中的门铃空间。第一个PCI总线通过第一个PCI网络适配器耦合到计算机网络，该PCI网络适配器处理写入事务并将其发送到网络。第二PCI总线通过第二PCI网络适配器耦合到计算机网络，第二PCI网络适配器从网络接收写入事务，并将写入事务转换为中断消息给第二处理器。

3. 发明授权

US06678758B2 Dynamic queuing for read/write requests 有权
标题翻译：动态排队读/写请求
公开(公告)号：US06678758B2
公开(公告)日：2004-01-13
申请号：US09778649
申请日：2001-02-05
申请人： Jeffrey D. Larson , Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie
发明人： Jeffrey D. Larson , Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie
IPC分类号： G06F1314
CPC分类号： G06F13/387
摘要： A PCI (peripheral component interconnect) network adaptor manages read/write requests through the establishment of dynamic queues. The PCI network adaptor establishes a unique queue for each destination node that enables the requests for each node to be processed separately. The PCI network adaptor determines whether a remote read/write request should be added to the linked list for the destination node of the request or whether the request should be rejected. If the number of pending requests for the destination node is below a predetermined threshold and the entire buffer is not full, then the request is added to the linked list for the destination node. Otherwise, the request is rejected. For write requests, if the request is added to the linked list for the destination node, then any pending read requests for that node are aborted.
摘要翻译： PCI（外围组件互连）网络适配器通过建立动态队列来管理读/写请求。 PCI网络适配器为每个目标节点建立一个唯一的队列，使每个节点的请求能够单独处理。 PCI网络适配器确定是否应将远程读/写请求添加到请求的目标节点的链接列表中，还是请求被拒绝。如果目的地节点的未决请求数量低于预定阈值并且整个缓冲器未满，则将该请求添加到目的地节点的链表。否则，请求被拒绝。对于写入请求，如果将请求添加到目标节点的链接列表，则该节点的任何未决读取请求将被中止。

4. 发明授权

US06901451B1 PCI bridge over network 失效
标题翻译： PCI桥接网络
公开(公告)号：US06901451B1
公开(公告)日：2005-05-31
申请号：US09703477
申请日：2000-10-31
申请人： Takashi Miyoshi , Jeffrey D. Larson , Hirohide Sugahara , Takeshi Horie
发明人： Takashi Miyoshi , Jeffrey D. Larson , Hirohide Sugahara , Takeshi Horie
IPC分类号： G06F13/36 , G06F13/40 , G06F15/16 , H04L12/40
CPC分类号： G06F13/4027
摘要： One embodiment of the present invention provides a method for communicating transaction request information from a PCI environment over a network. Another embodiment of the present invention provides a method for communicating request packet information from a network to a PCI environment. Another embodiment of the present invention provides a system for communicating transaction request information from a PCI environment over a network. Another embodiment of the present invention provides a system for communicating request packet information from a network to a PCI environment.
摘要翻译：本发明的一个实施例提供了一种用于通过网络从PCI环境传送交易请求信息的方法。本发明的另一实施例提供了一种用于将请求分组信息从网络传送到PCI环境的方法。本发明的另一实施例提供一种用于通过网络从PCI环境传送交易请求信息的系统。本发明的另一个实施例提供一种用于将请求分组信息从网络传送到PCI环境的系统。

5. 发明授权

US06804673B2 Access assurance for remote memory access over network 有权
标题翻译：通过网络进行远程存储器访问的访问保证
公开(公告)号：US06804673B2
公开(公告)日：2004-10-12
申请号：US09839954
申请日：2001-04-19
申请人： Hirohide Sugahara , Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie
发明人： Hirohide Sugahara , Jeffrey D. Larson , Takashi Miyoshi , Takeshi Horie
IPC分类号： G06F700
CPC分类号： G06F13/387 , Y10S707/99932
摘要： A method and system provide access assurance regarding an RDMA transaction. The system comprises an initiating device and a target device placed across a network. The initiating device and the target device are coupled to a first and a second buses, respectively. The first and the second buses are coupled to the network router through a first and a second network adaptors. An RDMA space and an associated access assurance space are assigned to the target device in the memory space of the first bus. The initiating device may RDMA the target device by directly reading from or writing into the RDMA space assigned to the target device. To obtain access assurance information regarding the RDMA transaction, the initiator performs a read from the assurance space associated with the RDMA space of the target device in the memory space of the first bus.
摘要翻译：方法和系统提供关于RDMA事务的访问保证。该系统包括通过网络放置的发起设备和目标设备。发起设备和目标设备分别耦合到第一和第二总线。第一和第二总线通过第一和第二网络适配器耦合到网络路由器。 RDMA空间和相关的访问保证空间被分配给第一总线的存储器空间中的目标设备。启动设备可以通过直接从分配给目标设备的RDMA空间读取或写入目标设备来RDMA目标设备。为了获得关于RDMA事务的访问保证信息，启动器从与第一总线的存储器空间中的目标设备的RDMA空间相关联的保证空间执行读取。

6. 发明授权

US06732212B2 Launch raw packet on remote interrupt 有权
标题翻译：在远程中断时启动原始数据包
公开(公告)号：US06732212B2
公开(公告)日：2004-05-04
申请号：US09785071
申请日：2001-02-14
申请人： Hirohide Sugahara , Takashi Miyoshi , Jeffrey D. Larson , Takeshi Horie
发明人： Hirohide Sugahara , Takashi Miyoshi , Jeffrey D. Larson , Takeshi Horie
IPC分类号： G06F1332
CPC分类号： G06F13/24 , G06F2213/2418
摘要： One embodiment of the present invention provides a method for processing a remote interrupt signal or a remote event. Another embodiment of the present invention provides a system for issuing a raw packet over a network in response to a remote interrupt or a remote event. Another embodiment of the present invention provides a network interface system configured to issue interrupt requests over a network.
摘要翻译：本发明的一个实施例提供一种用于处理远程中断信号或远程事件的方法。本发明的另一个实施例提供了一种用于响应于远程中断或远程事件通过网络发出原始分组的系统。本发明的另一个实施例提供一种被配置为通过网络发出中断请求的网络接口系统。

7. 发明授权

US06799219B1 Method and apparatus for avoiding starvation in computer network 有权
标题翻译：避免计算机网络中的饥饿的方法和装置
公开(公告)号：US06799219B1
公开(公告)日：2004-09-28
申请号：US09653154
申请日：2000-08-31
申请人： Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie , Jeffrey D. Larson
发明人： Hirohide Sugahara , Takashi Miyoshi , Takeshi Horie , Jeffrey D. Larson
IPC分类号： G06F1516
CPC分类号： H04L47/15 , H04L47/70 , H04L47/745 , H04L47/821 , H04L47/826
摘要： A method and apparatus for avoiding starvation at an initiator node in a computer network to which are connected at least one target node which provides service and a plurality of initiator nodes which request service from the target node. The method includes: when a request is received from the initiator node during a period that the target node is unable to provide service, returning a reject reply by attaching thereto reject time information that matches the period; when the target node is in a state capable of providing service, preferentially accepting a retry request carrying older reject time information; and when the target node is in the state capable of providing service, returning a reject reply by attaching thereto new reject time information in response to any first request received before retry requests arising from previously rejected requests are all accepted.
摘要翻译：一种用于避免在计算机网络中的发起者节点处的饥饿的方法和装置，至少一个提供服务的目标节点和从目标节点请求服务的多个发起方节点连接到该节点。该方法包括：当在目标节点不能提供服务的时段期间从发起者节点接收到请求时，通过附加拒绝回复的拒绝时间信息返回拒绝回复; 当目标节点处于能够提供服务的状态时，优先地接收携带较早拒绝时间信息的重试请求; 并且当目标节点处于能够提供服务的状态时，响应于在先前拒绝的请求引起的重试请求之前接收到的任何第一请求全部被接受，通过附加到新的拒绝时间信息来返回拒绝答复。

8. 发明授权

US5890217A Coherence apparatus for cache of multiprocessor 失效
标题翻译：多处理器缓存的一致性设备
公开(公告)号：US5890217A
公开(公告)日：1999-03-30
申请号：US598243
申请日：1996-02-07
申请人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
发明人： Akira Kabemoto , Naohiro Shibata , Toshiyuki Muta , Takayuki Shimamura , Hirohide Sugahara , Junji Nishioka , Takatsugu Sasaki , Satoshi Shinohara , Yozo Nakayama , Jun Sakurai , Hiroaki Ishihata , Takeshi Horie , Toshiyuki Shimizu
IPC分类号： G06F12/08 , G06F15/17 , G06F13/00
CPC分类号： G06F12/0817 , G06F12/0831 , G06F2212/2542
摘要： A plurality of processors, each with caches provided for a plurality of processor modules and a local storage in which a main storage is distributed and arranged are mutually connected through an internal snoop bus. The processor modules are mutually connected through a second system bus. By using two separate buses, cache coherence operations within a processor group is kept separate from cache coherence operations outside the processor group.
摘要翻译：多个处理器，每个处理器具有为多个处理器模块提供的高速缓存和其中分配和布置主存储器的本地存储器通过内部监听总线相互连接。处理器模块通过第二系统总线相互连接。通过使用两个单独的总线，处理器组内的高速缓存一致性操作与处理器组之外的高速缓存一致性操作保持分开。

9. 发明授权

US07246335B2 Analyzing substrate noise 有权
标题翻译：分析衬底噪声
公开(公告)号：US07246335B2
公开(公告)日：2007-07-17
申请号：US11058900
申请日：2005-02-15
申请人： Rajeev Murgai , Subodh M. Reddy , Takashi Miyoshi , Takeshi Horie , Mehdi B. Tahoori
发明人： Rajeev Murgai , Subodh M. Reddy , Takashi Miyoshi , Takeshi Horie , Mehdi B. Tahoori
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5036
摘要： In one embodiment, a method for analyzing substrate noise includes applying a static timing analysis (STA) algorithm to a description of a digital circuit. Application of the STA algorithm generates timing information on one or more gates in the digital circuit. The method also includes applying a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit. Application of the CWG algorithm generates a current waveform. The method also includes generating a reduced model (RM) of the digital circuit for simulation according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit. Simulation of the RM of the digital circuit generates an indication of noise in a substrate associated with the digital circuit.
摘要翻译：在一个实施例中，用于分析衬底噪声的方法包括将静态时序分析（STA）算法应用于数字电路的描述。 STA算法的应用在数字电路中的一个或多个门上产生定时信息。该方法还包括将电流波形生成（CWG）算法应用于数字电路的描述，数字电路中的一个或多个门上的定时信息以及数字电路中的开关活动的描述。 CWG算法的应用产生电流波形。该方法还包括根据数字电路的描述，电流波形和与数字电路相关联的封装的模型，生成用于模拟的数字电路的简化模型（RM）。数字电路的RM的仿真产生与数字电路相关联的衬底中的噪声的指示。

10. 发明申请

US20060184904A1 Analyzing substrate noise 有权
标题翻译：分析衬底噪声
公开(公告)号：US20060184904A1
公开(公告)日：2006-08-17
申请号：US11058900
申请日：2005-02-15
申请人： Rajeev Murgai , Subodh Reddy , Takashi Miyoshi , Takeshi Horie , Mehdi Tahoori
发明人： Rajeev Murgai , Subodh Reddy , Takashi Miyoshi , Takeshi Horie , Mehdi Tahoori
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In one embodiment, a method for analyzing substrate noise includes applying a static timing analysis (STA) algorithm to a description of a digital circuit. Application of the STA algorithm generates timing information on one or more gates in the digital circuit. The method also includes applying a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit. Application of the CWG algorithm generates a current waveform. The method also includes generating a reduced model (RM) of the digital circuit for simulation according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit. Simulation of the RM of the digital circuit generates an indication of noise in a substrate associated with the digital circuit.
摘要翻译：在一个实施例中，用于分析衬底噪声的方法包括将静态时序分析（STA）算法应用于数字电路的描述。 STA算法的应用在数字电路中的一个或多个门上产生定时信息。该方法还包括将电流波形生成（CWG）算法应用于数字电路的描述，数字电路中的一个或多个门上的定时信息以及数字电路中的开关活动的描述。 CWG算法的应用产生电流波形。该方法还包括根据数字电路的描述，电流波形和与数字电路相关联的封装的模型，生成用于模拟的数字电路的简化模型（RM）。数字电路的RM的仿真产生与数字电路相关联的衬底中的噪声的指示。

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