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1. 发明授权

US06590825B2 Non-volatile flash fuse element 有权
标题翻译：非易失性闪存保险丝元件
公开(公告)号：US06590825B2
公开(公告)日：2003-07-08
申请号：US10002036
申请日：2001-11-01
申请人： Hieu Van Tran , William John Saiki , George J. Korsh , Sakhawat M. Khan
发明人： Hieu Van Tran , William John Saiki , George J. Korsh , Sakhawat M. Khan
IPC分类号： G11C700
CPC分类号： G11C29/027 , G11C16/04 , G11C16/0441 , G11C29/02 , G11C29/50
摘要： A non-volatile flash fuse element and an array of such elements include fuses coupled to the input of a latch arranged as a differential comparator for constant current differential sensing. The fuse element includes a margining circuit that provides differential mass fuse margining. The margining circuit also allows the fuses to be stressed and screened. The fuse elements also provide constant current parallel programming.
摘要翻译：非易失性闪存熔丝元件和这种元件的阵列包括耦合到作为用于恒定电流差动感测的差分比较器的锁存器的输入的熔丝。保险丝元件包括提供差分质量保险丝边缘的边缘电路。保险丝电路还允许保险丝受到压力和屏蔽。熔丝元件还提供恒流并行编程。

2. 发明授权

US06992937B2 Column redundancy for digital multilevel nonvolatile memory 有权
标题翻译：数字多级非易失性存储器的列冗余
公开(公告)号：US06992937B2
公开(公告)日：2006-01-31
申请号：US10628979
申请日：2003-07-28
申请人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki , George J. Korsh
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C11/5621 , G11C16/04 , G11C29/027 , G11C29/50004 , G11C29/82 , G11C2029/0409
摘要： A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to read or write contents to a multilevel bit memory cell and compare the read cell content to reference voltage levels to determine the data stored in the corresponding memory cell. Likewise, similar functions are performed by the redundant y-driver circuit for the redundant memory array. During the verification of the contents of the memory cell, if the read voltage is outside a certain margin requirement for a level of the reference voltage, a signal is generated in real time so that data from the bad y-driver is not output and data from the redundant y-driver corresponding to the redundant memory array is read out. The memory array system may also include a fractional multilevel redundancy.
摘要翻译：数字多电平位存储器阵列系统包括常规存储器阵列和冗余存储器阵列。常规y驱动器对应于每个存储器阵列以将内容读取或写入多级位存储器单元，并将读取的单元内容与参考电压电平进行比较，以确定存储在相应存储器单元中的数据。类似的功能由冗余的y驱动电路执行，用于冗余存储器阵列。在验证存储单元的内容期间，如果读取电压超出参考电压电平的一定余量要求，则实时生成信号，以便不输出来自不良y驱动器的数据和数据从对应于冗余存储器阵列的冗余y驱动器读出。存储器阵列系统还可以包括分数多级冗余。

3. 发明授权

US06967524B2 High voltage generation and regulation system for digital multilevel nonvolatile memory 有权
标题翻译：用于数字多级非易失性存储器的高压发生和调节系统
公开(公告)号：US06967524B2
公开(公告)日：2005-11-22
申请号：US10990786
申请日：2004-11-16
申请人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
发明人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C16/30 , H02M3/07 , G05F1/10
CPC分类号： H02M3/07 , G11C16/30
摘要： A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.
摘要翻译：高压发生器提供具有不同调节电压电平的高电压信号。电荷泵产生高电压，并且包括具有上电辅助二极管的正交相位正向和反向Vt消除高电压自偏压电荷泵。高压串联调节器产生高电压电平，并包括压摆率增强和可调二极管调节。嵌套回路调节器消除了分流调节。

4. 发明授权

US07061295B2 Ring oscillator for digital multilevel non-volatile memory 有权
标题翻译：用于数字多电平非易失性存储器的环形振荡器
公开(公告)号：US07061295B2
公开(公告)日：2006-06-13
申请号：US10991301
申请日：2004-11-16
申请人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
发明人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G06F1/04
CPC分类号： H02M3/07 , G11C16/30
摘要： An oscillator that can be used within a high voltage generation and regulation system for non-volatile memory. The system may comprise a charge pump that may have at least one pump and an oscillator. In one aspect the oscillator provides clock signals to the pump. The output of the oscillator may be disabled without turning off the clock generation. The oscillator may be a ring oscillator. In one aspect, the ring oscillator and the output stage may comprise inverters with a capacitor coupled to the output of the inverter. In one aspect, the ratio of the capacitors in the ring oscillator to the capacitor in the output stage determine the phase shift between the two clock signals. In another aspect, the capacitance of the capacitors are identical and a bias applied the ring oscillator and the output stage are radioed to adjust the phase between the two clock signals.
摘要翻译：可用于非易失性存储器的高压发生和调节系统中的振荡器。该系统可以包括可以具有至少一个泵和振荡器的电荷泵。在一个方面，振荡器向泵提供时钟信号。可以禁用振荡器的输出而不关闭时钟产生。振荡器可以是环形振荡器。在一个方面，环形振荡器和输出级可以包括具有耦合到反相器的输出的电容器的反相器。在一个方面，环形振荡器中的电容器与输出级中的电容器的比率决定了两个时钟信号之间的相移。在另一方面，电容器的电容是相同的，并且施加环形振荡器的偏置，并且输出级被无线电以调节两个时钟信号之间的相位。

5. 发明授权

US07038538B2 Folded cascode high voltage operational amplifier with class AB source follower output stage 有权
公开(公告)号：US07038538B2
公开(公告)日：2006-05-02
申请号：US10376989
申请日：2003-02-26
申请人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki
发明人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki
IPC分类号： H03G5/16
CPC分类号： H03F3/45192
摘要： An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement. A local power supply pre-filter provides a filtered local high voltage to the differential input stage and stages that provide the fixed and adaptive voltage bias signals.

6. 发明授权

US06867638B2 High voltage generation and regulation system for digital multilevel nonvolatile memory 有权
公开(公告)号：US06867638B2
公开(公告)日：2005-03-15
申请号：US10044273
申请日：2002-01-10
申请人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
发明人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C16/30 , H02M3/07 , G05F1/10
CPC分类号： H02M3/07 , G11C16/30
摘要： A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

7. 发明授权

US06590453B2 Folded cascode high voltage operational amplifier with class AB source follower output stage 有权
公开(公告)号：US06590453B2
公开(公告)日：2003-07-08
申请号：US09960589
申请日：2001-09-21
申请人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki
发明人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki
IPC分类号： H03F345
CPC分类号： H03F3/45192
摘要： An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement. A local power supply pre-filter provides a filtered local high voltage to the differential input stage and stages that provide the fixed and adaptive voltage bias signals.

8. 发明申请

US20090096507A1 Integrated Semiconductor Metal-Insulator-Semiconductor Capacitor 审中-公开
标题翻译：集成半导体金属绝缘体 - 半导体电容器
公开(公告)号：US20090096507A1
公开(公告)日：2009-04-16
申请号：US12270604
申请日：2008-11-13
申请人： Feng Gao , Changyuan Chen , Vishal Sarin , William John Saiki , Hieu Van Tran , Dana Lee
发明人： Feng Gao , Changyuan Chen , Vishal Sarin , William John Saiki , Hieu Van Tran , Dana Lee
IPC分类号： H03K3/01
CPC分类号： H01L27/0805 , H01L27/0811 , H01L29/94
摘要： An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.
摘要翻译：集成的MIS电容器具有两个基本相同的MIS电容器。第一电容器包括在半导体衬底中与第一导电类型的沟道区相邻的第一导电类型的第一区域。半导体衬底具有第二导电类型。栅电极与第一电容器的沟道区隔离并隔开。第二电容器基本上与第一电容器相同，并且形成在相同的半导体衬底中。第一电容器的栅电极电连接到第二电容器的第一区域，并且第二电容器的栅极电连接到第一电容器的第一区域。以这种方式，电容器以反并联配置连接。具有高电容密度，低工艺复杂性，双极性操作，低电压和温度系数，低外部寄生电阻和电容以及用于可与现有半导体工艺结合的模拟设计的良好匹配特性的电容器。

9. 发明授权

US07038960B2 High speed and high precision sensing for digital multilevel non-volatile memory system 有权
标题翻译：数字多级非易失性存储器系统的高速和高精度感测
公开(公告)号：US07038960B2
公开(公告)日：2006-05-02
申请号：US10241442
申请日：2002-09-10
申请人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
发明人： Hieu Van Tran , Jack Edward Frayer , William John Saiki , Michael Stephen Briner
IPC分类号： G11C7/00
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/28
摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.
摘要翻译：数字多电平非易失性存储器包括大量感测系统，其包括布置在存储器单元的相邻子阵列上的多个读出放大器。读出放大器包括高速负载，宽输出范围中间级和低阻抗输出驱动器。高速负载提供高速感应。宽输出范围在比较节点上提供高速的感测余量。低阻抗输出驱动器驱动差分比较器的高噪声负载。耦合到读出放大器的输入和输出的预充电电路增加了感测速度。差分比较器具有包括模拟引导的架构。参考读出放大器具有与差分放大器相同的结构，以减少偏移误差。参考差分放大器还包括用于检测冗余单元和参考单元的内容的信号复用。

10. 发明授权

US06813194B2 Bias distribution network for digital multilevel nonvolatile flash memory 有权
标题翻译：用于数字多电平非易失性闪存的偏置分配网络
公开(公告)号：US06813194B2
公开(公告)日：2004-11-02
申请号：US10044821
申请日：2002-01-10
申请人： Hieu Van Tran , William John Saiki
发明人： Hieu Van Tran , William John Saiki
IPC分类号： G11C1606
CPC分类号： G11C29/021 , G11C11/5621 , G11C16/04 , G11C16/30 , G11C29/02 , G11C29/028 , G11C29/50 , G11C2029/5006
摘要： A memory device includes an array of memory cells arranged in rows and columns with a portion of the rows of the memory cells being divided into segments. A global bias circuit generates a plurality of first bias currents. Each of a plurality of local bias networks includes a local bias circuit that generates a plurality of second bias currents in response to a corresponding one of the plurality of first bias currents, and includes a plurality of segment bias circuits that each generates a third bias current. Each segment bias circuit is adjacent to a corresponding segment of the memory cells. Each segment bias circuit provides a ground feedback signal to the local bias circuit, which adjusts the second bias current in response to the ground feedback signal. The segment bias circuits are disposed in geometric positions in the segments.
摘要翻译：存储器件包括排列成行和列的存储器单元的阵列，其中存储单元的行的一部分被划分成段。全局偏置电路产生多个第一偏置电流。多个局部偏置网络中的每一个包括本地偏置电路，其响应于多个第一偏置电流中的相应一个产生多个第二偏置电流，并且包括多个段偏置电路，每个偏置电路产生第三偏置电流。每个段偏置电路与存储单元的相应段相邻。每个段偏置电路向局部偏置电路提供接地反馈信号，该偏置电路响应于接地反馈信号调整第二偏置电流。段偏置电路设置在段中的几何位置。

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