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1. 发明授权

US06992937B2 Column redundancy for digital multilevel nonvolatile memory 有权
标题翻译：数字多级非易失性存储器的列冗余
公开(公告)号：US06992937B2
公开(公告)日：2006-01-31
申请号：US10628979
申请日：2003-07-28
申请人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki , George J. Korsh
IPC分类号： G11C11/00
CPC分类号： G11C29/50 , G11C11/5621 , G11C16/04 , G11C29/027 , G11C29/50004 , G11C29/82 , G11C2029/0409
摘要： A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to read or write contents to a multilevel bit memory cell and compare the read cell content to reference voltage levels to determine the data stored in the corresponding memory cell. Likewise, similar functions are performed by the redundant y-driver circuit for the redundant memory array. During the verification of the contents of the memory cell, if the read voltage is outside a certain margin requirement for a level of the reference voltage, a signal is generated in real time so that data from the bad y-driver is not output and data from the redundant y-driver corresponding to the redundant memory array is read out. The memory array system may also include a fractional multilevel redundancy.
摘要翻译：数字多电平位存储器阵列系统包括常规存储器阵列和冗余存储器阵列。常规y驱动器对应于每个存储器阵列以将内容读取或写入多级位存储器单元，并将读取的单元内容与参考电压电平进行比较，以确定存储在相应存储器单元中的数据。类似的功能由冗余的y驱动电路执行，用于冗余存储器阵列。在验证存储单元的内容期间，如果读取电压超出参考电压电平的一定余量要求，则实时生成信号，以便不输出来自不良y驱动器的数据和数据从对应于冗余存储器阵列的冗余y驱动器读出。存储器阵列系统还可以包括分数多级冗余。

2. 发明授权

US06590825B2 Non-volatile flash fuse element 有权
标题翻译：非易失性闪存保险丝元件
公开(公告)号：US06590825B2
公开(公告)日：2003-07-08
申请号：US10002036
申请日：2001-11-01
申请人： Hieu Van Tran , William John Saiki , George J. Korsh , Sakhawat M. Khan
发明人： Hieu Van Tran , William John Saiki , George J. Korsh , Sakhawat M. Khan
IPC分类号： G11C700
CPC分类号： G11C29/027 , G11C16/04 , G11C16/0441 , G11C29/02 , G11C29/50
摘要： A non-volatile flash fuse element and an array of such elements include fuses coupled to the input of a latch arranged as a differential comparator for constant current differential sensing. The fuse element includes a margining circuit that provides differential mass fuse margining. The margining circuit also allows the fuses to be stressed and screened. The fuse elements also provide constant current parallel programming.
摘要翻译：非易失性闪存熔丝元件和这种元件的阵列包括耦合到作为用于恒定电流差动感测的差分比较器的锁存器的输入的熔丝。保险丝元件包括提供差分质量保险丝边缘的边缘电路。保险丝电路还允许保险丝受到压力和屏蔽。熔丝元件还提供恒流并行编程。

3. 发明授权

US06967524B2 High voltage generation and regulation system for digital multilevel nonvolatile memory 有权
标题翻译：用于数字多级非易失性存储器的高压发生和调节系统
公开(公告)号：US06967524B2
公开(公告)日：2005-11-22
申请号：US10990786
申请日：2004-11-16
申请人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
发明人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C16/30 , H02M3/07 , G05F1/10
CPC分类号： H02M3/07 , G11C16/30
摘要： A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.
摘要翻译：高压发生器提供具有不同调节电压电平的高电压信号。电荷泵产生高电压，并且包括具有上电辅助二极管的正交相位正向和反向Vt消除高电压自偏压电荷泵。高压串联调节器产生高电压电平，并包括压摆率增强和可调二极管调节。嵌套回路调节器消除了分流调节。

4. 发明授权

US07061295B2 Ring oscillator for digital multilevel non-volatile memory 有权
标题翻译：用于数字多电平非易失性存储器的环形振荡器
公开(公告)号：US07061295B2
公开(公告)日：2006-06-13
申请号：US10991301
申请日：2004-11-16
申请人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
发明人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G06F1/04
CPC分类号： H02M3/07 , G11C16/30
摘要： An oscillator that can be used within a high voltage generation and regulation system for non-volatile memory. The system may comprise a charge pump that may have at least one pump and an oscillator. In one aspect the oscillator provides clock signals to the pump. The output of the oscillator may be disabled without turning off the clock generation. The oscillator may be a ring oscillator. In one aspect, the ring oscillator and the output stage may comprise inverters with a capacitor coupled to the output of the inverter. In one aspect, the ratio of the capacitors in the ring oscillator to the capacitor in the output stage determine the phase shift between the two clock signals. In another aspect, the capacitance of the capacitors are identical and a bias applied the ring oscillator and the output stage are radioed to adjust the phase between the two clock signals.
摘要翻译：可用于非易失性存储器的高压发生和调节系统中的振荡器。该系统可以包括可以具有至少一个泵和振荡器的电荷泵。在一个方面，振荡器向泵提供时钟信号。可以禁用振荡器的输出而不关闭时钟产生。振荡器可以是环形振荡器。在一个方面，环形振荡器和输出级可以包括具有耦合到反相器的输出的电容器的反相器。在一个方面，环形振荡器中的电容器与输出级中的电容器的比率决定了两个时钟信号之间的相移。在另一方面，电容器的电容是相同的，并且施加环形振荡器的偏置，并且输出级被无线电以调节两个时钟信号之间的相位。

5. 发明授权

US07038538B2 Folded cascode high voltage operational amplifier with class AB source follower output stage 有权
公开(公告)号：US07038538B2
公开(公告)日：2006-05-02
申请号：US10376989
申请日：2003-02-26
申请人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki
发明人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki
IPC分类号： H03G5/16
CPC分类号： H03F3/45192
摘要： An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement. A local power supply pre-filter provides a filtered local high voltage to the differential input stage and stages that provide the fixed and adaptive voltage bias signals.

6. 发明授权

US06867638B2 High voltage generation and regulation system for digital multilevel nonvolatile memory 有权
公开(公告)号：US06867638B2
公开(公告)日：2005-03-15
申请号：US10044273
申请日：2002-01-10
申请人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
发明人： William John Saiki , Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C16/30 , H02M3/07 , G05F1/10
CPC分类号： H02M3/07 , G11C16/30
摘要： A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

7. 发明授权

US06590453B2 Folded cascode high voltage operational amplifier with class AB source follower output stage 有权
公开(公告)号：US06590453B2
公开(公告)日：2003-07-08
申请号：US09960589
申请日：2001-09-21
申请人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki
发明人： Hieu Van Tran , Sakhawat M. Khan , William John Saiki
IPC分类号： H03F345
CPC分类号： H03F3/45192
摘要： An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement. A local power supply pre-filter provides a filtered local high voltage to the differential input stage and stages that provide the fixed and adaptive voltage bias signals.

8. 发明授权

US07471581B2 Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory 有权
标题翻译：用于多电平数字非易失性存储器的宽动态范围和高速电压模式感测
公开(公告)号：US07471581B2
公开(公告)日：2008-12-30
申请号：US11726913
申请日：2007-03-22
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

9. 发明授权

US06865099B2 Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory 有权
标题翻译：用于多电平数字非易失性存储器的宽动态范围和高速电压模式感测
公开(公告)号：US06865099B2
公开(公告)日：2005-03-08
申请号：US10211886
申请日：2002-08-01
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C11/56 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C27/00 , G11C5/06
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

10. 发明授权

US06519180B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
公开(公告)号：US06519180B2
公开(公告)日：2003-02-11
申请号：US09929370
申请日：2001-08-13
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

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