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1. 发明授权

US07035151B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
公开(公告)号：US07035151B2
公开(公告)日：2006-04-25
申请号：US10868614
申请日：2004-06-14
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C8/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

2. 发明授权

US06504754B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
公开(公告)号：US06504754B2
公开(公告)日：2003-01-07
申请号：US09898582
申请日：2001-07-02
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

3. 发明授权

US06396742B1 Testing of multilevel semiconductor memory 有权
标题翻译：多层半导体存储器测试
公开(公告)号：US06396742B1
公开(公告)日：2002-05-28
申请号：US09627917
申请日：2000-07-28
申请人： George J. Korsh , Sakhawat M. Khan , Hieu Van Tran
发明人： George J. Korsh , Sakhawat M. Khan , Hieu Van Tran
IPC分类号： G11C1604
CPC分类号： G11C29/028 , G11C11/56 , G11C11/5621 , G11C29/50 , G11C2029/5004
摘要： In accordance with an embodiment of the present invention, a method for testing a multilevel memory includes: performing an erase operation to place a plurality of memory cells in an erased state; programming a state of each cell in a group of the plurality of cells to within a first range of voltages; if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing; and if a state of each cell in the group of cells verifies to within the first range of voltages: applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages.
摘要翻译：根据本发明的实施例，一种用于测试多电平存储器的方法包括：执行擦除操作以将多个存储单元置于擦除状态; 将所述多个单元的组中的每个单元的状态编程为在第一电压范围内; 如果所述单元组中的一个或多个单元格中的每一个的状态未被验证到所述第一电压范围内，则至少将所述一个或多个单元识别为故障; 并且如果所述单元组中的每个单元的状态验证为在所述第一电压范围内：施加预定数量的编程脉冲以进一步将所述单元组中的每个单元的状态编程到第二电压范围内; 以及验证所述单元组中的每个单元的状态是否被编程超过所述第二电压范围。

4. 发明授权

US4519849A Method of making EPROM cell with reduced programming voltage 失效
标题翻译：降低编程电压的方法制作EPROM单元
公开(公告)号：US4519849A
公开(公告)日：1985-05-28
申请号：US515990
申请日：1983-07-22
申请人： George J. Korsh , Mark A. Holler , George Perlegos , Paolo Gargini
发明人： George J. Korsh , Mark A. Holler , George Perlegos , Paolo Gargini
IPC分类号： H01L21/28 , H01L29/788 , H01L21/22 , H01L21/26
CPC分类号： H01L21/28273 , H01L29/7885
摘要： An improved floating gate MOS EPROM cell which is programmable at a lower potential (12 volts) than prior art devices which often require 25 volts. The oxide thickness between the floating gate and overlying control gate is thicker at the edges of the floating gate than in the central portion. The thicker oxide at the edges prevents uncontrolled DC erasing. This allows a thinner oxide to be used in the central portion and provides the increased capacitance coupling needed for programming at a lower potential.
摘要翻译：改进的浮置栅极EPROM单元，其可以比通常需要25伏特的现有技术器件更低的电位（12伏特）可编程。浮动栅极和上覆控制栅极之间的氧化物厚度在浮动栅极的边缘处比在中心部分更厚。边缘处的较厚氧化物可防止不受控制的直流擦除。这允许在中心部分使用更薄的氧化物，并提供在较低电位下编程所需的增加的电容耦合。

5. 发明授权

US07566915B2 Guard ring extension to prevent reliability failures 有权
标题翻译：防护环扩展以防止可靠性故障
公开(公告)号：US07566915B2
公开(公告)日：2009-07-28
申请号：US11648250
申请日：2006-12-29
申请人： Nicole Meier Chang , George J. Korsh , Shafqat Ahmed , John Nugent , Ed Nabighian
发明人： Nicole Meier Chang , George J. Korsh , Shafqat Ahmed , John Nugent , Ed Nabighian
IPC分类号： H01L29/74
CPC分类号： H01L23/585 , H01L22/32 , H01L23/3178 , H01L23/3192 , H01L23/562 , H01L2924/0002 , H01L2924/09701 , Y10S148/07 , H01L2924/00
摘要： An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
摘要翻译：本发明的一个实施例是一种防止半导体器件可靠性故障的技术。在具有顶部金属层的保护环上的聚酰亚胺层中图案化沟槽。钝化层在沟槽的底部蚀刻。在蚀刻的钝化层上的沟槽上沉积覆盖层。覆盖层和顶部金属层形成机械强界面以防止裂纹扩展。

6. 发明授权

US06519180B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
公开(公告)号：US06519180B2
公开(公告)日：2003-02-11
申请号：US09929370
申请日：2001-08-13
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

7. 发明授权

US5815439A Stabilization circuits and techniques for storage and retrieval of single or multiple digital bits per memory cell 失效
标题翻译：用于每个存储器单元存储和检索单个或多个数字位的稳定电路和技术
公开(公告)号：US5815439A
公开(公告)日：1998-09-29
申请号：US640367
申请日：1996-04-30
申请人： George J. Korsh , Sakhawat M. Khan
发明人： George J. Korsh , Sakhawat M. Khan
IPC分类号： G11C16/02 , G11C11/56 , H03H1/00 , G11C7/00
CPC分类号： G11C11/5657 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/565 , G11C16/3418 , G11C16/3431
摘要： An integrated circuit memory system having memory cells capable of storing multiple bits per cell is described. The memory system has a restoring operation in which a memory cells' stored charge, which may drift from its initially set condition, is maintained within one of a plurality of predetermined levels corresponding to digital bits of information and defined by a set of special reference voltage values. The memory system has mini-programming and mini-erasing operations to move only the amount of charge into and out of the memory cell sufficient to keep the charge within the predetermined levels. The memory system also has an operation for high speed programming of the memory cells and an erasing operation to narrow the charge distribution of erased memory cells for increasing the spread, and safety margins, between the predetermined levels.
摘要翻译：描述了具有能够存储每个单元的多个位的存储器单元的集成电路存储器系统。存储器系统具有恢复操作，其中可能从其初始设置状态漂移的存储器单元的存储电荷保持在对应于数字信息位的多个预定电平之一中，并由一组特殊参考电压价值观。存储器系统具有微型编程和微型擦除操作，以仅将足够的电荷量进入和离开存储器单元以将电荷保持在预定水平。存储器系统还具有用于存储器单元的高速编程的操作以及擦除操作以减小擦除的存储器单元的电荷分布，以增加预定电平之间的扩展以及安全裕度。

8. 发明授权

US4949139A Transistor construction for low noise output driver 失效
标题翻译：用于低噪声输出驱动器的晶体管结构
公开(公告)号：US4949139A
公开(公告)日：1990-08-14
申请号：US242708
申请日：1988-09-09
申请人： George J. Korsh , Edward Hui
发明人： George J. Korsh , Edward Hui
IPC分类号： H01L29/423 , H03K19/003
CPC分类号： H01L29/4238 , H01L29/42396 , H03K19/00361
摘要： A transistor construction having a gate electrode meandering in a serpentine manner between interlacked comb-like drain and sources electrodes. The construction is equivalent to parallel transistors with series-connected gates, and the resistivity of the gate electrode forms a RC delay line in which transistors furthest from the gate drivers lag behind those which are closest. Accordingly, the transistor construction turns on or off gradually. The construction is useful as part of a CMOS output driver to memory chips and the like where the inductance of bondwires and the package leads normally cause noise spikes. The transistor construction reduces the current slew rate during switching so that less noise occurs on the chip supply lines. Another embodiment is made up of up to four parallel connected blocks of series-connected-gates. Multiple gate turn-off drivers are provided in a modified output driver, connected in parallel to each series-connected gate block, to insure that the transistor block turns off more rapidly than it turns on.
摘要翻译：一种晶体管结构，其具有栅极电极，以蛇形方式在嵌入式梳状漏极和源极之间曲折。该结构相当于具有串联栅极的并联晶体管，栅电极的电阻率形成RC延迟线，其中最远离栅极驱动器的晶体管滞后于最接近晶体管的晶体管。因此，晶体管结构逐渐打开或关闭。该结构对于存储芯片等的CMOS输出驱动器的一部分是有用的，其中，焊丝和电感线的电感通常引起噪声尖峰。晶体管结构降低了切换期间的电流转换速率，从而在芯片供电线路上产生较少的噪声。另一个实施例由多达四个串联连接的并联连接的块组成。在修改的输出驱动器中提供多个栅极关断驱动器，并联连接到每个串联连接的栅极块，以确保晶体管块比其导通更快地关断。

9. 发明申请

US20100187528A1 GUARD RING EXTENSION TO PREVENT RELIABILITY FAILURES 有权
标题翻译：保护环延伸以防止可靠性故障
公开(公告)号：US20100187528A1
公开(公告)日：2010-07-29
申请号：US12727010
申请日：2010-03-18
申请人： Nicole Meier Chang , George J. Korsh , Shafqat Ahmed , John Nugent , Ed Nabighian
发明人： Nicole Meier Chang , George J. Korsh , Shafqat Ahmed , John Nugent , Ed Nabighian
IPC分类号： H01L23/48
CPC分类号： H01L23/585 , H01L22/32 , H01L23/3178 , H01L23/3192 , H01L23/562 , H01L2924/0002 , H01L2924/09701 , Y10S148/07 , H01L2924/00
摘要： An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
摘要翻译：本发明的一个实施例是一种防止半导体器件可靠性故障的技术。在具有顶部金属层的保护环上的聚酰亚胺层中图案化沟槽。钝化层在沟槽的底部蚀刻。在蚀刻的钝化层上的沟槽上沉积覆盖层。封盖层和顶部金属层形成机械强界面以防止裂纹扩展。

10. 发明申请

US20080157284A1 Guard ring extension to prevent reliability failures 有权
标题翻译：防护环扩展以防止可靠性故障
公开(公告)号：US20080157284A1
公开(公告)日：2008-07-03
申请号：US11648250
申请日：2006-12-29
申请人： Nicole Meier Chang , George J. Korsh , Shafqat Ahmed , John Nugent , Ed Nabighian
发明人： Nicole Meier Chang , George J. Korsh , Shafqat Ahmed , John Nugent , Ed Nabighian
IPC分类号： H01L29/00 , H01L21/44
CPC分类号： H01L23/585 , H01L22/32 , H01L23/3178 , H01L23/3192 , H01L23/562 , H01L2924/0002 , H01L2924/09701 , Y10S148/07 , H01L2924/00
摘要： An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
摘要翻译：本发明的一个实施例是一种防止半导体器件可靠性故障的技术。在具有顶部金属层的保护环上的聚酰亚胺层中图案化沟槽。钝化层在沟槽的底部蚀刻。在蚀刻的钝化层上的沟槽上沉积覆盖层。封盖层和顶部金属层形成机械强界面以防止裂纹扩展。

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