专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090164731A1 SYSTEM AND METHOD FOR OPTIMIZING NEIGHBORING CACHE USAGE IN A MULTIPROCESSOR ENVIRONMENT 有权
标题翻译：在多处理器环境中优化相邻高速缓存的系统和方法
公开(公告)号：US20090164731A1
公开(公告)日：2009-06-25
申请号：US11959652
申请日：2007-12-19
申请人： Hien Minh Le , Jason Alan Cox , Robert John Dorsey , Richard Nicholas , Eric Francis Robinson , Thuong Quang Truong
发明人： Hien Minh Le , Jason Alan Cox , Robert John Dorsey , Richard Nicholas , Eric Francis Robinson , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit. The first PU determines whether to transmit the castout cache line to the second PU based on the response. And, in the event the first PU determines to transmit the castout cache line to the second PU, the first PU transmits the castout cache line to the second PU.
摘要翻译：用于管理数据的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作，每个PU具有包括多个高速缓存行的高速缓存，每个高速缓存行具有多个相关性状态之一，以及每个PU耦合到多个PU中的至少另一个。第一PU选择第一PU的第一高速缓存中的多条高速缓存线的转出高速缓存线，以使第一高速缓冲存储器被抛弃。第一PU向第二PU发送请求，其中第二PU是第一PU的相邻PU，并且该请求包括所选择的丢弃高速缓存行的第一地址和第一相关性状态。第二PU确定第一地址是否与第二PU中的任何高速缓存行的地址相匹配。第二PU基于第二高速缓存中的多条高速缓存行中的每一条的一致性状态以及是否存在地址命中，向第一PU发送响应。第一PU确定是否根据该响应将丢弃高速缓存行发送到第二PU。并且，在第一PU确定将丢弃高速缓存行发送到第二PU的情况下，第一PU将丢弃高速缓存行发送到第二PU。

2. 发明授权

US07836257B2 System and method for cache line replacement selection in a multiprocessor environment 失效
标题翻译：多处理器环境中缓存线替换选择的系统和方法
公开(公告)号：US07836257B2
公开(公告)日：2010-11-16
申请号：US11959804
申请日：2007-12-19
申请人： Robert John Dorsey , Jason Alan Cox , Hien Minh Le , Richard Nicholas , Eric Francis Robinson , Thuong Quang Truong
发明人： Robert John Dorsey , Jason Alan Cox , Hien Minh Le , Richard Nicholas , Eric Francis Robinson , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/0813 , G06F12/0831 , G06F12/128
摘要： A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.
摘要翻译：用于管理高速缓存的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作。第一PU确定第一PU的第一高速缓存中的多条高速缓存线之一必须被第一数据块替换，并且确定第一数据块是否是来自多个PU中的另一个的受害缓存行。在第一数据块不是来自多个PU中的另一个的第一数据块的情况下，第一高速缓存不包含一致性状态的高速缓存行无效，并且第一高速缓存包含移动的一致性状态的高速缓存行，第一PU选择移动的一致性状态的高速缓存行，将第一数据块存储在所选择的高速缓存行中，并更新第一数据块的一致性状态。

3. 发明申请

US20090164735A1 System and Method for Cache Coherency In A Multiprocessor System 有权
标题翻译：多处理器系统中缓存一致性的系统和方法
公开(公告)号：US20090164735A1
公开(公告)日：2009-06-25
申请号：US11959793
申请日：2007-12-19
申请人： Richard Nicholas , Jason Alan Cox , Robert John Dorsey , Hien Minh Le , Eric Francis Robinson , Thuong Quang Truong
发明人： Richard Nicholas , Jason Alan Cox , Robert John Dorsey , Hien Minh Le , Eric Francis Robinson , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813 , G06F12/084
摘要： A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU.
摘要翻译：用于维持高速缓存一致性的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作，每个PU具有高速缓存，并且每个PU耦合到多个PU中的至少另一个。第一PU接收用于存储在第一PU的第一高速缓存中的第一数据块。第一个PU将第一个数据块存储在第一个缓存中。第一PU将第一相关性状态和第一标签分配给第一数据块，其中第一相关性状态是指示第一PU是否已经访问了第一数据块的多个相关性状态之一。多个相关性状态还指示在第一PU未访问第一数据块的情况下，第一PU从相邻PU接收到第一数据块。

4. 发明申请

US20090164736A1 System and Method for Cache Line Replacement Selection in a Multiprocessor Environment 失效
标题翻译：多处理器环境中缓存线替换选择的系统和方法
公开(公告)号：US20090164736A1
公开(公告)日：2009-06-25
申请号：US11959804
申请日：2007-12-19
申请人： Robert John Dorsey , Jason Alan Cox , Hien Minh Le , Richard Nicholas , Eric Francis Robinson , Thuong Quang Truong
发明人： Robert John Dorsey , Jason Alan Cox , Hien Minh Le , Richard Nicholas , Eric Francis Robinson , Thuong Quang Truong
IPC分类号： G06F12/08
CPC分类号： G06F12/127 , G06F12/0813 , G06F12/0831 , G06F12/128
摘要： A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.
摘要翻译：用于管理高速缓存的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作。第一PU确定第一PU的第一高速缓存中的多条高速缓存线之一必须被第一数据块替换，并且确定第一数据块是否是来自多个PU中的另一个的受害缓存行。在第一数据块不是来自多个PU中的另一个的第一数据块的情况下，第一高速缓存不包含一致性状态的高速缓存行无效，并且第一高速缓存包含移动的一致性状态的高速缓存行，第一PU选择移动的一致性状态的高速缓存行，将第一数据块存储在所选择的高速缓存行中，并更新第一数据块的一致性状态。

5. 发明授权

US08397029B2 System and method for cache coherency in a multiprocessor system 有权
标题翻译：多处理器系统中高速缓存一致性的系统和方法
公开(公告)号：US08397029B2
公开(公告)日：2013-03-12
申请号：US11959793
申请日：2007-12-19
申请人： Richard Nicholas , Jason Alan Cox , Robert John Dorsey , Hien Minh Le , Eric Francis Robinson , Thuong Quang Truong
发明人： Richard Nicholas , Jason Alan Cox , Robert John Dorsey , Hien Minh Le , Eric Francis Robinson , Thuong Quang Truong
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813 , G06F12/084
摘要： A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU.
摘要翻译：用于维持高速缓存一致性的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作，每个PU具有高速缓存，并且每个PU耦合到多个PU中的至少另一个。第一PU接收用于存储在第一PU的第一高速缓存中的第一数据块。第一个PU将第一个数据块存储在第一个缓存中。第一PU将第一相关性状态和第一标签分配给第一数据块，其中第一相关性状态是指示第一PU是否已经访问了第一数据块的多个相关性状态之一。多个相关性状态还指示在第一PU未访问第一数据块的情况下，第一PU从相邻PU接收到第一数据块。

6. 发明授权

US08296520B2 System and method for optimizing neighboring cache usage in a multiprocessor environment 有权
标题翻译：用于优化多处理器环境中的相邻缓存使用的系统和方法
公开(公告)号：US08296520B2
公开(公告)日：2012-10-23
申请号：US11959652
申请日：2007-12-19
申请人： Hien Minh Le , Jason Alan Cox , Robert John Dorsey , Richard Nicholas , Eric Francis Robinson , Thuong Quang Truong
发明人： Hien Minh Le , Jason Alan Cox , Robert John Dorsey , Richard Nicholas , Eric Francis Robinson , Thuong Quang Truong
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit. The first PU determines whether to transmit the castout cache line to the second PU based on the response. And, in the event the first PU determines to transmit the castout cache line to the second PU, the first PU transmits the castout cache line to the second PU.
摘要翻译：用于管理数据的方法在具有系统存储器和多个处理单元（PU）的数据处理系统中操作，每个PU具有包括多个高速缓存行的高速缓存，每个高速缓存行具有多个相关性状态之一，以及每个PU耦合到多个PU中的至少另一个。第一PU选择第一PU的第一高速缓存中的多条高速缓存线的转出高速缓存线，以使第一高速缓冲存储器被抛弃。第一PU向第二PU发送请求，其中第二PU是第一PU的相邻PU，并且该请求包括所选择的丢弃高速缓存行的第一地址和第一相关性状态。第二PU确定第一地址是否与第二PU中的任何高速缓存行的地址相匹配。第二PU基于第二高速缓存中的多条高速缓存行中的每一条的一致性状态以及是否存在地址命中，向第一PU发送响应。第一PU确定是否根据该响应将丢弃高速缓存行发送到第二PU。并且，在第一PU确定将丢弃高速缓存行发送到第二PU的情况下，第一PU将丢弃高速缓存行发送到第二PU。

7. 发明授权

US07080269B2 Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains 失效
标题翻译：在具有多个时钟域的设计中实现省电睡眠模式的方法和装置
公开(公告)号：US07080269B2
公开(公告)日：2006-07-18
申请号：US10439040
申请日：2003-05-15
申请人： Yoanna Baumgartner , Sundeep Chadha , Richard Nicholas Iachetta, Jr. , Hien Minh Le , Kirk Edward Morrow
发明人： Yoanna Baumgartner , Sundeep Chadha , Richard Nicholas Iachetta, Jr. , Hien Minh Le , Kirk Edward Morrow
IPC分类号： G06F1/26
CPC分类号： G06F1/3228 , G06F1/12 , G06F1/324 , Y02D10/126
摘要： A system and a method are provided for implementing a power-saving sleep mode in a synchronous circuit core having multiple clock domains including primary and secondary clock domains. The primary clock domain has states of awake, asleep, doze, and waking. The doze and waking states are transient states between the awake and asleep states. One or more secondary clock domains each have states of secondary awake and secondary asleep. The doze and waking states are used to eliminate race conditions between the primary and secondary clock domains. If the core has two or more secondary clock domains, the secondary clock domains each have an additional state of sleep-pending. The sleep-pending state is a transient state between the secondary awake and secondary asleep states. One or more synchronization logics are coupled between the primary and secondary clock domains.
摘要翻译：提供了一种用于在具有包括主时钟域和次时钟域的多个时钟域的同步电路核中实现节电睡眠模式的系统和方法。主时钟域具有清醒，睡眠，打盹和醒来的状态。打盹和醒来的状态是唤醒和睡眠状态之间的瞬态状态。一个或多个次级时钟域各自具有二次唤醒和次要睡眠状态。打盹和醒来的状态被用来消除主时钟和次要时钟域之间的竞争条件。如果核心具有两个或多个次级时钟域，则辅助时钟域各自具有待处理的附加状态。睡眠挂起状态是二次唤醒和二次睡眠状态之间的暂态。一个或多个同步逻辑耦合在主时钟域和次时钟域之间。

8. 发明申请

US20070012562A1 Method and apparatus for sputtering onto large flat panels 有权
标题翻译：用于溅射到大平板上的方法和装置
公开(公告)号：US20070012562A1
公开(公告)日：2007-01-18
申请号：US11484333
申请日：2006-07-11
申请人： Hien Minh Le , Akihiro Hosokawa , Avi Tepman
发明人： Hien Minh Le , Akihiro Hosokawa , Avi Tepman
IPC分类号： C23C14/00 , C23C14/32
CPC分类号： C23C14/35 , H01J37/3408 , H01J37/3455
摘要： A rectangular magnetron placed at the back of a rectangular sputtering target for coating a rectangular panel and having magnets of opposed polarities arranged to form a gap therebetween corresponding to a plasma track adjacent the target which extends in a closed serpentine or spiral loop. The spiral may have a large number of wraps and the closed loop may be folded before wrapping. The magnetron has a size only somewhat less than that of the target and is scanned in the two perpendicular directions of the target with a scan length of, for example, about 100 mm for a 2 m target corresponding to at least the separation of the gap between parallel portions of the loop. A central ferromagnetic shim beneath some magnets in the loop may compensate for vertical droop. The magnetron may be scanned in two alternating double-Z patterns rotated 90° between them.
摘要翻译：放置在矩形溅射靶的背面的矩形磁控管，用于涂覆矩形面板并且具有相对极性的磁体，所述磁体布置成在对应于邻近靶的等离子体轨道之间形成间隙，所述等离子体轨道以闭合的蛇形或螺旋形环路延伸。螺旋可以具有大量的包装，并且闭合的环可以在包装之前折叠。磁控管的尺寸仅稍低于目标的尺寸，并且在目标的两个垂直方向上扫描，对于对应于至少间隙间隔的2m靶的扫描长度例如为约100mm 在环路的平行部分之间。环路中一些磁铁下方的中心铁磁垫片可以补偿垂直下垂。磁控管可以以它们之间旋转90°的两个交替的双Z图案进行扫描。

9. 发明申请

US20090210566A1 MULTI-CHIP DIGITAL SYSTEM SIGNAL IDENTIFICATION APPARATUS 失效
标题翻译：多芯片数字系统信号识别装置
公开(公告)号：US20090210566A1
公开(公告)日：2009-08-20
申请号：US12032990
申请日：2008-02-18
申请人： Robert Christopher Dixon , John Wayne Hartfiel , Hien Minh Le , Tung Nguyen Pham
发明人： Robert Christopher Dixon , John Wayne Hartfiel , Hien Minh Le , Tung Nguyen Pham
IPC分类号： G06F3/00
CPC分类号： G06F1/22 , G01R31/318572 , G06F11/006 , G06F11/2236
摘要： The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.
摘要翻译：本发明提供一种系统。该系统包括多个控制器，每个控制器包括至少一个输出引脚和多个输入引脚，并且被配置为通过多个输入引脚中的一个或多个接收自识别控制信号，并且发送控制器自识别信号通过输出引脚基于自识别控制信号。每个输出引脚耦合到外部系统。处理器耦合到多个控制器中的每一个的多个输入引脚中的第一输入引脚，并被配置为产生自识别控制信号并将自识别控制信号发送到多个控制器。

10. 发明授权

US07716546B2 System and method for improved LBIST power and run time 有权
标题翻译：改善LBIST功率和运行时间的系统和方法
公开(公告)号：US07716546B2
公开(公告)日：2010-05-11
申请号：US11866787
申请日：2007-10-03
申请人： Hien Minh Le , Robert Christopher Dixon , Luis Carlos Medina , Tung Nguyen Pham
发明人： Hien Minh Le , Robert Christopher Dixon , Luis Carlos Medina , Tung Nguyen Pham
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/27
摘要： A method for improved Logic Built-In Self-Test (LBIST) includes providing a plurality of control signal sets, by an LBIST controller, to an LBIST domain comprising a plurality of LBIST satellite modules. Each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves the LBIST channel scan and LBIST sequence operations for each of the LBIST satellite modules, through the plurality of control signal sets.A test system includes a Logic Built-In Self-Test (LBIST) domain comprising a plurality of LBIST satellite modules. An LBIST controller couples to the LBIST domain and provides a plurality of control signal sets to the LBIST domain, wherein each of the plurality of LBIST satellite modules receives an individual one of the plurality of control signal sets. The LBIST controller interleaves LBIST channel scan operations for each of the LBIST satellite modules, through the plurality of control signal sets.
摘要翻译：一种用于改进逻辑内置自检（LBIST）的方法包括：由LBIST控制器将多个控制信号组提供给包括多个LBIST卫星模块的LBIST域。多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描和LBIST序列操作。测试系统包括包括多个LBIST卫星模块的逻辑内置自测（LBIST）域。 LBIST控制器耦合到LBIST域并向LBIST域提供多个控制信号组，其中多个LBIST卫星模块中的每一个接收多个控制信号组中的一个。 LBIST控制器通过多个控制信号组来交织每个LBIST卫星模块的LBIST信道扫描操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式