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1. 发明授权

US06308239B1 Interface switching apparatus and switching control method 失效
标题翻译：接口切换装置和切换控制方法
公开(公告)号：US06308239B1
公开(公告)日：2001-10-23
申请号：US08964603
申请日：1997-11-05
申请人： Hideyuki Osakada , Ryuichi Hattori , Yukihiro Seki
发明人： Hideyuki Osakada , Ryuichi Hattori , Yukihiro Seki
IPC分类号： G06F1314
CPC分类号： G06F13/4022 , G06F2213/4004
摘要： In order to share a device among a plurality of hosts, a switching section is adapted to select one of the hosts by switching and connect it to the device by a serial interface. The switching section can be controlled from the particular host through at least an interface cable. When the switching section switches the host to be connected with the device, power continues to be supplied to the device. Further, a connection recognition protocol to be transmitted from the device when beginning to supply power to the device is transmitted from the switching section. In this way, a quick switching operation free of protocol contradictions is made possible without causing any hardware resetting of the device.
摘要翻译：为了在多个主机之间共享设备，切换部分适于通过切换选择一个主机，并通过串行接口将其连接到设备。可以通过至少一个接口电缆从特定主机控制切换部分。当切换部分切换与设备连接的主机时，继续向设备供电。此外，从切换部发送从开始向设备供电时从设备发送的连接识别协议。以这种方式，可以实现没有协议矛盾的快速切换操作，而不会导致设备的任何硬件重置。

2. 发明授权

US06622195B2 Interface switching apparatus and switching control method 失效
标题翻译：接口切换装置和切换控制方法
公开(公告)号：US06622195B2
公开(公告)日：2003-09-16
申请号：US09875990
申请日：2001-06-08
申请人： Hideyuki Osakada , Ryuichi Hattori , Yukihiro Seki
发明人： Hideyuki Osakada , Ryuichi Hattori , Yukihiro Seki
IPC分类号： G06F1314
CPC分类号： G06F13/4022 , G06F2213/4004
摘要： In order to share a device among a plurality of hosts, a switching section is adapted to select one of the hosts by switching and connect it to the device by a serial interface. The switching section can be controlled from the particular host through at least an interface cable. When the switching section switches the host to be connected with the device, power continues to be supplied to the device. Further, a connection recognition protocol to be transmitted from the device when beginning to supply power to the device is transmitted from the switching section. In this way, a quick switching operation free of protocol contradictions is made possible without causing any hardware resetting of the device.
摘要翻译：为了在多个主机之间共享设备，切换部分适于通过切换选择一个主机，并通过串行接口将其连接到设备。可以通过至少一个接口电缆从特定主机控制切换部分。当切换部分切换与设备连接的主机时，继续向设备供电。此外，从切换部发送从开始向设备供电时从设备发送的连接识别协议。以这种方式，可以实现没有协议矛盾的快速切换操作，而不会导致设备的任何硬件重置。

3. 发明授权

US06061238A Information processing apparatus, method of arranging components of the apparatus, and heat sink 有权
标题翻译：信息处理装置，该装置的部件的配置方法以及散热器
公开(公告)号：US06061238A
公开(公告)日：2000-05-09
申请号：US340138
申请日：1999-06-28
申请人： Hideyuki Osakada , Yukihiro Seki , Tsunehiro Tobita , Junichi Taguri , Hiroshi Mochizuki
发明人： Hideyuki Osakada , Yukihiro Seki , Tsunehiro Tobita , Junichi Taguri , Hiroshi Mochizuki
IPC分类号： G06F1/18 , G06F1/20 , H02M3/00 , H05K1/14 , H05K7/20
CPC分类号： H05K1/14 , H02M3/00 , H05K7/209
摘要： An information processing apparatus includes a plurality of processor boards arranged parallelly on the main board and the DC--DC converters for generating operation voltages for processor devices each disposed between the adjacent processor boards. Further, a metal plate with high thermal conductivity is placed in close contact with an area of each of the processor boards where devices generating a large amount of heat are mounted. Heat dissipating fins are joined to the surface of each of the metal plates so that when the processor boards are mounted on the main board, the heat dissipating fins do not contact the DC--DC converter. The heat dissipating fins and the DC--DC converters are arranged so that they are vertically disposed one over the other with respect to the main board.
摘要翻译：信息处理装置包括并排布置在主板上的多个处理器板和用于产生处理器设备的操作电压的DC-DC转换器，每个处理器设置在相邻的处理器板之间。此外，具有高导热性的金属板被放置成与安装有产生大量热量的装置的每个处理器板的区域紧密接触。散热翅片与每个金属板的表面接合，使得当处理器板安装在主板上时，散热片不接触DC-DC转换器。散热翅片和DC-DC转换器被布置成使得它们相对于主板垂直地设置在另一个上。

4. 发明授权

US06584530B2 Information processing system, bus arbiter, and bus controlling method 有权
标题翻译：信息处理系统，总线仲裁器和总线控制方法
公开(公告)号：US06584530B2
公开(公告)日：2003-06-24
申请号：US10173819
申请日：2002-06-19
申请人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
发明人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
IPC分类号： G06F1338
CPC分类号： G06F13/364
摘要： The present invention provides a means for preventing execution of a transaction such as main storage access from obstruction by bus competition with low-speed IO access and improving the bus occupation efficiency. Apparatus for preventing execution of a transaction such as storage access from obstruction by bus competition with low-speed IO access. The invention includes a first bus, a second bus, a plurality of modules connected to both buses, a bus conversion unit for performing protocol conversion of information between both buses, a bus arbiter for arbitrating a bus occupation right request of a bus master, and a storage for storing access data up to a predetermined amount when the access destination is a predetermined module. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus occupation right request, the bus arbiter refers to the access destination information and the data storage status of the storage and decides whether to give a bus occupation right to the bus master.
摘要翻译：本发明提供了一种用于防止执行诸如主存储器访问的事务的方法，以便通过具有低速IO访问的总线竞争阻塞，并且提高总线占用效率。用于防止执行诸如存储访问以避免总线阻塞的事务的装置竞争与低速IO访问。本发明包括第一总线，第二总线，连接到两个总线的多个模块，用于在两个总线之间执行信息协议转换的总线转换单元，用于仲裁总线主机的总线占用权请求的总线仲裁器和存储器，用于当访问目的地是预定模块时存储高达预定量的访问数据。每个总线主机输出接入目的地信息，当总线仲裁器判断其中一个总线主机发出总线占用权请求时，总线仲裁器参考存储的访问目的地信息和数据存储状态，并决定是否给出总线占领权掌握公交车主。

5. 发明授权

US06275436B1 Flash memory control method and apparatus processing system therewith 有权
公开(公告)号：US06275436B1
公开(公告)日：2001-08-14
申请号：US09577371
申请日：2000-05-23
申请人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
发明人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
IPC分类号： G11C800
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0644 , G06F3/0656 , G06F3/0679 , G06F3/068 , G06F11/1433 , G06F11/1441 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F2003/0694 , G06F2212/2022 , G06F2212/312 , G11C29/789 , G11C29/82
摘要： A control method and system when a flash memory is used. as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address. The control section is responsive to the interface information, the first management information, and the second management information for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory. The consecutive address generation means and the sector address storage means output the physical sector address and the consecutively generated addresses to the first nonvolatile memory and the volatile memory when data at the physical sector address is output from the first nonvolatile memory or when data at the physical sector address is input to the volatile memory.

6. 发明授权

US06421279B1 Flash memory control method and apparatus processing system therewith 有权
标题翻译：闪存控制方法和装置处理系统
公开(公告)号：US06421279B1
公开(公告)日：2002-07-16
申请号：US09927493
申请日：2001-08-13
申请人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
发明人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
IPC分类号： G11C800
CPC分类号： G11C29/765 , G06F3/0601 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0644 , G06F3/0656 , G06F3/0679 , G06F3/068 , G06F11/1433 , G06F11/1441 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F2003/0694 , G06F2212/2022 , G06F2212/312 , G11C29/789 , G11C29/82
摘要： A semiconductor file system features a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating correspondence between physical and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information. The controller determines a physical sector address. The control section is for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory.
摘要翻译：半导体文件系统具有电可擦除的第一非易失性存储器，不电可擦除的第二非易失性存储器，易失性存储器，控制器和控制部分，其控制控制器，其中对应于从外部系统指定的逻辑地址的物理地址是访问。第一非易失性存储器存储用于执行操作的外部系统的数据，指示物理和逻辑地址之间的对应关系的第一管理信息以及指示第一非易失性存储器的状态的第二管理信息。第二非易失性存储器先前存储接口信息。控制器确定物理扇区地址。控制部分用于控制来自/外部系统的数据的输入/输出，并用于从易失性存储器中的外部系统暂时将写数据存储到第一非易失性存储器中，然后将写入数据从易失性存储器传送到第一非易失性存储器记忆。

7. 发明授权

US6078520A Flash memory control method and information processing system therewith 有权
标题翻译：闪存控制方法和信息处理系统
公开(公告)号：US6078520A
公开(公告)日：2000-06-20
申请号：US357931
申请日：1999-07-21
申请人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
发明人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
IPC分类号： G06F11/14 , G06F12/08 , G11C29/00 , G11C17/00
CPC分类号： G11C29/765 , G06F11/1433 , G06F12/08 , G06F12/0802 , G06F12/0866 , G11C29/789 , G11C29/82 , G06F2212/2022 , G06F2212/312
摘要： A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller has a control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.
摘要翻译：当闪存用作信息处理系统中的半导体盘或主存储器时的控制方法和系统。半导体文件系统包括电可擦除的第一非易失性存储器，不电可擦除的第二非易失性存储器，易失性存储器，控制存储器的控制器和控制控制器的控制部分，其中对应于由访问一个外部系统。第一非易失性存储器存储用于执行操作的外部系统的数据，指示存储数据的物理地址与逻辑地址之间的对应关系的第一管理信息，以及指示第一非易失性存储器的状态的第二管理信息。第二非易失性存储器预先存储从外部系统输入和输出数据所需的接口信息以及数据的只读数据。控制器具有控制装置，用于当数据从第一非易失性存储器输出时或当数据被输入到易失性存储器时，确定形成物理地址的预定高位的物理扇区地址，用于存储确定的物理扇区地址的装置，以及用于在由所述物理扇区地址确定的扇区中连续生成地址的装置。

8. 发明授权

US6021455A Method and system for arbitrating a bus according to the status of a buffer and destination information 失效
标题翻译：根据缓冲区和目的地信息的状态仲裁总线的方法和系统
公开(公告)号：US6021455A
公开(公告)日：2000-02-01
申请号：US708324
申请日：1996-09-05
申请人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
发明人： Nobukazu Kondo , Koichi Okazawa , Yukihiro Seki , Ryuichi Hattori , Masaya Umemura , Shigemi Adachi , Kouichi Nakai , Takashi Moriyama
IPC分类号： G06F13/36 , G06F13/362 , G06F13/364 , G06F13/00
CPC分类号： G06F13/364
摘要： An information processing system includes a first bus, a second bus, a plurality of modules connected to both buses, a bus arbiter for arbitrating a bus access request of a bus master, and a storage means for storing access data up to a predetermined amount for one of modules when access destination information indicates that said module is the access destination. Each bus master outputs access destination information and when the bus arbiter judges that one of the bus masters issues a bus access request when it performs an access operation, the bus arbiter refers to whether the predetermined amount of access destination information is fully stored in the storage means, and decides whether or not to give a bus access to the bus master.
摘要翻译：一种信息处理系统，包括第一总线，第二总线，连接到两个总线的多个模块，用于仲裁总线主机的总线访问请求的总线仲裁器，以及用于存储高达预定量的访问数据的存储装置，当访问目的地信息指示所述模块是访问目的地时，模块之一。每个总线主机输出接入目的地信息，当总线仲裁器在执行访问操作时判断总线主机之一发出总线访问请求时，总线仲裁器是指预定量的访问目的地信息是否完全存储在存储器中意味着，并决定是否给总线访问总线主控。

9. 发明授权

US5781434A Control system for communication apparatus 失效
标题翻译：通讯设备控制系统
公开(公告)号：US5781434A
公开(公告)日：1998-07-14
申请号：US543145
申请日：1995-10-13
申请人： Tsunehiro Tobita , Yukihiro Seki , Ryuichi Hattori , Yuji Miyagawa , Shigeru Sakurai , Michiyuki Suzuki , Ichiro Ote
发明人： Tsunehiro Tobita , Yukihiro Seki , Ryuichi Hattori , Yuji Miyagawa , Shigeru Sakurai , Michiyuki Suzuki , Ichiro Ote
IPC分类号： G06F11/30 , G06F13/00 , H04L12/12 , G05B19/10
CPC分类号： H04L12/12 , Y02B60/33 , Y02B60/34
摘要： An information processing system includes a modem communicating with a remote console through a telephone line, an information processing apparatus communicating with the remote console through the modem, a service processor, a power supply continuously supplying power to the modem and the service processor, a power supply supplying power to the information processing apparatus according to commands from the service processor, and a switch connecting the modem to the service processor or the information processing apparatus in accordance with a switching signal from the service processor. The service processor controls the switch to connect the modem to the service processor when the information processing apparatus power supply is in the off state. The service processor outputs a power-on command when the service processor receives a power-on request of the information processing apparatus power supply from the remote console through the telephone line and the modem and the switch connects the modem to the information processing apparatus when the execution of the power-on command is completed.
摘要翻译：信息处理系统包括通过电话线与远程控制台通信的调制解调器，通过调制解调器与远程控制台通信的信息处理设备，服务处理器，向调制解调器和服务处理器连续供电的电源，功率根据来自服务处理器的命令向信息处理设备供电，以及根据来自服务处理器的切换信号将调制解调器连接到服务处理器或信息处理设备的交换机。当信息处理设备电源处于关闭状态时，服务处理器控制交换机将调制解调器连接到服务处理器。当服务处理器通过电话线路和调制解调器从远程控制台接收到信息处理设备电源的接通请求时，服务处理器输出开机命令，并且交换机将调制解调器连接到信息处理设备时上电指令的执行完成。

10. 发明授权

US5530673A Flash memory control method and information processing system therewith 失效
标题翻译：闪存控制方法和信息处理系统
公开(公告)号：US5530673A
公开(公告)日：1996-06-25
申请号：US225313
申请日：1994-04-08
申请人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
发明人： Tsunehiro Tobita , Jun Kitahara , Takashi Tsunehiro , Kunihiro Katayama , Ryuichi Hattori , Yukihiro Seki , Hajime Yamagami , Takashi Totsuka , Takeshi Wada , Yosio Takaya , Manabu Saito , Kenichi Kaki , Takao Okubo , Takashi Kikuchi , Masamichi Kishi , Takeshi Suzuki , Shigeru Kadowaki
IPC分类号： G06F3/06 , G06F11/14 , G06F12/08 , G11C29/00 , G11C16/06 , G06F12/16
CPC分类号： G11C29/765 , G06F11/1433 , G06F11/1441 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F3/0601 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0644 , G06F3/0656 , G06F3/0679 , G06F3/068 , G11C29/789 , G11C29/82 , G06F2003/0694 , G06F2212/2022 , G06F2212/312
摘要： A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address.
摘要翻译：当闪存用作信息处理系统中的半导体盘或主存储器时的控制方法和系统。半导体文件系统包括电可擦除的第一非易失性存储器，不电可擦除的第二非易失性存储器，易失性存储器，控制存储器的控制器和控制控制器的控制部分，其中对应于由访问一个外部系统。第一非易失性存储器存储用于执行操作的外部系统的数据，指示存储数据的物理地址与逻辑地址之间的对应关系的第一管理信息，以及指示第一非易失性存储器的状态的第二管理信息。第二非易失性存储器预先存储从外部系统输入和输出数据所需的接口信息以及数据的只读数据。控制器包括控制装置，用于当数据从第一非易失性存储器输出时或当数据被输入到易失性存储器时，确定形成物理地址的预定高位的物理扇区地址，存储确定的物理扇区地址的装置，以及用于连续地产生由物理扇区地址确定的扇区中的地址的装置。

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