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1. 发明授权

US07196368B2 Semiconductor memory arrangements with crown shaped capacitor arrangements trenched in interlayer dielectric film 失效
标题翻译：具有冠状电容器布置的半导体存储器布置在层间绝缘膜中沟槽
公开(公告)号：US07196368B2
公开(公告)日：2007-03-27
申请号：US10914223
申请日：2004-08-10
申请人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
发明人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/108 , H01L27/10814 , H01L27/10817 , H01L27/10882 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L28/90
摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.
摘要翻译：在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器）和埋入布线层（9和11）形成在电容器下面。由于电容器不是形成在半导体衬底中而是在其上形成，所以存在可以形成电容器的区域的空间，并且通过使用全局字线的布线层（9和11）难以形成布线，选择线。由于在周边电路区域与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域并与电容器（33）的一侧接触，外围电路区域和存储单元区域之间的台阶高度显着降低。

2. 发明授权

US06798005B2 Semiconductor memory device having large storage capacity and minimal step height between memory cell and peripheral circuits 有权
标题翻译：存储单元与外围电路之间存储容量大，步距高的半导体存储器件
公开(公告)号：US06798005B2
公开(公告)日：2004-09-28
申请号：US10206215
申请日：2002-07-29
申请人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
发明人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/108 , H01L27/10814 , H01L27/10817 , H01L27/10882 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L28/90
摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.
摘要翻译：在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器）和埋入布线层（9和11）形成在电容器下面。由于电容器不是形成在半导体衬底中而是在其上形成，因此通过使用用于全局字线的布线层（9和11），可以形成电容器并且难以形成布线的难度减小，随着在外围电路区域中与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域中并与电容器的侧面接触（33），外围电路区域和存储单元区域之间的台阶高度显着降低。

3. 发明授权

US6130449A Semiconductor memory device and a method for fabricating the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US6130449A
公开(公告)日：2000-10-10
申请号：US943592
申请日：1997-10-03
申请人： Hideyuki Matsuoka , Shinichiro Kimura , Toshiaki Yamanaka
发明人： Hideyuki Matsuoka , Shinichiro Kimura , Toshiaki Yamanaka
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/92 , H01L29/40 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10882 , H01L27/10894 , H01L27/10814 , H01L27/10852 , H01L28/84 , H01L28/91
摘要： A semiconductor memory device and a method of fabricating the same are provided, in which an interlayer film which only covers a peripheral circuit region except a memory cell array region is formed above the peripheral circuit region to reduce a topological difference between both regions after bitlines are formed, therefore a semiconductor substrate which has a plain surface as a main one can be used as a starting body with no preliminary processing thereon and a shallow trench isolation technique can also be applied, besides interconnects to the peripheral circuit can be led up to the surface of the device through a multi-step plug connection and thereby processing of large aspect-ratio holes, stuffing of metal in the holes and the like are unnecessary and as a result reliability of the process is improved.
摘要翻译：提供一种半导体存储器件及其制造方法，其中仅在外围电路区域之上形成仅覆盖存储单元阵列区域的外围电路区域的层间膜，以减少位线之后的两个区域之间的拓扑差异因此，以普通表面为主要的半导体衬底可以用作起始体，而不需要预处理，并且还可以应用浅沟槽隔离技术，除了与外围电路的互连之外，还可以引导到通过多级插头连接装置的表面，从而处理大的纵横比孔，在孔中填充金属等，从而提高了工艺的可靠性。

4. 发明授权

US06791134B2 Semiconductor memory device and manufacturing method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06791134B2
公开(公告)日：2004-09-14
申请号：US10205421
申请日：2002-07-26
申请人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
发明人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/108 , H01L27/10814 , H01L27/10817 , H01L27/10882 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L28/90
摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.
摘要翻译：在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器）和埋入布线层（9和11）形成在电容器下面。由于电容器不是形成在半导体衬底中而是在其上形成，因此通过使用用于全局字线的布线层（9和11），可以形成电容器并且难以形成布线的难度减小，随着在外围电路区域中与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域中并与电容器的侧面接触（33），外围电路区域和存储单元区域之间的台阶高度显着降低。

5. 发明授权

US06677194B2 Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US06677194B2
公开(公告)日：2004-01-13
申请号：US10162573
申请日：2002-06-06
申请人： Toshiaki Yamanaka , Akio Nishida , Yasuko Yoshida , Shuji Ikeda , Kenichi Kuroda , Shiro Kamohara , Shinichiro Kimura , Eiichi Murakami , Hideyuki Matsuoka , Masataka Minami
发明人： Toshiaki Yamanaka , Akio Nishida , Yasuko Yoshida , Shuji Ikeda , Kenichi Kuroda , Shiro Kamohara , Shinichiro Kimura , Eiichi Murakami , Hideyuki Matsuoka , Masataka Minami
IPC分类号： H01L218238
CPC分类号： H01L21/823807 , H01L21/2652 , H01L21/823842 , H01L21/823892
摘要： A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.
摘要翻译：低阈值电压NMIS区域和高阈值电压PMIS区域由也用于阱形成的光致抗蚀剂掩模设置。使用具有用于NMIS和PMIS的开口的光致抗蚀剂掩模，通过一个离子注入步骤设置NMIS和PMIS区域。栅极氧化后，离子注入通过非晶硅膜导入孔，通道和栅电极。可以设置多个CMIS阈值电压，并且可以以减少数量的步骤使用光致抗蚀剂形成两个极性的栅电极。这解决了需要光掩模的问题，因为存在孔，通道阻挡件，栅电极和阈值电压控制的离子注入类型，因此制造步骤的数量和生产成本增加。

6. 发明授权

US06617205B1 Semiconductor storage device and process for manufacturing the same 失效
标题翻译：半导体存储装置及其制造方法
公开(公告)号：US06617205B1
公开(公告)日：2003-09-09
申请号：US09077100
申请日：1998-05-20
申请人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
发明人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/108 , H01L27/10814 , H01L27/10817 , H01L27/10882 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L28/90
摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.
摘要翻译：在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器）和埋入布线层（9和11）形成在电容器下面。由于电容器不是形成在半导体衬底中而是在其上形成，因此通过使用用于全局字线的布线层（9和11），可以形成电容器并且难以形成布线的难度减小，随着在外围电路区域中与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域中并与电容器的侧面接触（33），外围电路区域和存储单元区域之间的台阶高度显着降低。

7. 发明申请

US20050045933A1 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20050045933A1
公开(公告)日：2005-03-03
申请号：US10914223
申请日：2004-08-10
申请人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
发明人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/108 , H01L27/10814 , H01L27/10817 , H01L27/10882 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L28/90
摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.
摘要翻译：在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器）和埋入布线层（9和11）形成在电容器下面。由于电容器不是形成在半导体衬底中而是在其上形成，所以存在可以形成电容器的区域的空间，并且通过使用全局字线的布线层（9和11）难以形成布线，选择线。由于在周边电路区域与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域并与电容器（33）的一侧接触，外围电路区域和存储单元区域之间的台阶高度显着降低。

8. 发明授权

US06831316B1 Semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06831316B1
公开(公告)日：2004-12-14
申请号：US10009826
申请日：2002-03-19
申请人： Hideyuki Matsuoka , Takeshi Sakata , Shinichiro Kimura , Toshiaki Yamanaka , Tsuyoshi Kachi , Tomonori Sekiguchi
发明人： Hideyuki Matsuoka , Takeshi Sakata , Shinichiro Kimura , Toshiaki Yamanaka , Tsuyoshi Kachi , Tomonori Sekiguchi
IPC分类号： H01L4700
CPC分类号： H01L27/108 , H01L27/10894 , H01L27/10897
摘要： An existent DRAM memory cell comprises transistors as a switch and capacitors for accumulating storage charges in which the height of the capacitor has been increased more and more along with micro miniaturization, which directly leads to increase in the manufacturing cost. The invention of the present application provides a semiconductor memory device of a basic constitution in which a memory cell array having plural memory cells disposed on a semiconductor substrate and word lines and data lines for selecting the memory cells and a peripheral circuit at the periphery of the memory cell array wherein the memory cell comprises a multi-layer of a conductive layer, an insulating layer and plural semiconductor layers containing impurities, and a potential can be applied to the insulating layer enabling the tunneling effect. The invention of the present application concerns a memory cell not requiring capacitor and capable of being formed in simple steps.
摘要翻译：存在的DRAM存储单元包括作为开关的晶体管和用于累积存储电荷的电容器，其中电容器的高度随着微型化而逐渐增加，这直接导致制造成本的增加。本申请的发明提供了一种基本结构的半导体存储器件，其中具有设置在半导体衬底上的多个存储单元的存储单元阵列和用于选择存储单元的字线和数据线以及外围电路的外围电路存储单元阵列，其中存储单元包括导电层的多层，绝缘层和含有杂质的多个半导体层，并且可以将电位施加到能够实现隧道效应的绝缘层。本申请的发明涉及不需要电容器并能够以简单的步骤形成的存储单元。

9. 发明授权

US06376304B1 Semiconductor memory device and a method for fabricating the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06376304B1
公开(公告)日：2002-04-23
申请号：US09608154
申请日：2000-06-30
申请人： Hideyuki Matsuoka , Shinichiro Kimura , Toshiaki Yamanaka
发明人： Hideyuki Matsuoka , Shinichiro Kimura , Toshiaki Yamanaka
IPC分类号： H01L218242
CPC分类号： H01L27/10882 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： A semiconductor memory device and a method of fabricating the same are provided, in which an interlayer film which only covers a peripheral circuit region except a memory cell array is formed above the peripheral circuit region to reduce a topological difference between both regions after bitlines are formed; therefore, a semiconductor substrate which has a plain surface as a main one can be used as a starting body with no preliminary processing thereon and a shallow trench isolation technique can also be applied. Besides, interconnects to the peripheral circuit can be led up to the surface of the device through a multi-step plug connection and thereby processing of large aspect-ratio holes, the filling up of the holes with metal and the like are unnecessary and, as a result, reliability of the process is improved.
摘要翻译：提供一种半导体存储器件及其制造方法，其中在外围电路区域之上形成仅覆盖存储单元阵列外的外围电路区域的层间膜，以减少在形成位线之后的两个区域之间的拓扑差异 ; 因此，以普通表面为主要的半导体衬底可以用作起始体，而不需要预处理，也可以应用浅沟槽隔离技术。此外，与外围电路的互连可以通过多级插头连接引导到设备的表面，从而处理大的纵横比孔，用金属填充孔等是不必要的，因为结果，改进了该过程的可靠性。

10. 发明授权

US06900492B2 Integrated circuit device with P-type gate memory cell having pedestal contact plug and peripheral circuit 失效
标题翻译：具有P型栅极存储单元的集成电路器件具有基座接触插头和外围电路
公开(公告)号：US06900492B2
公开(公告)日：2005-05-31
申请号：US10164008
申请日：2002-06-07
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Shinichiro Kimura , Ryo Nagai , Satoru Yamada
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Shinichiro Kimura , Ryo Nagai , Satoru Yamada
IPC分类号： H01L27/108 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10894 , H01L21/76895 , H01L21/76897 , H01L21/823857 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L29/4941 , H01L29/6656
摘要： A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved.Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.
摘要翻译： DRAM存储单元的刷新特性得到改善，并且在周边形成的构成逻辑电路的MISFET的性能得到改善。存储单元区域中的每个栅电极由p型多晶硅形成，并且每个栅电极上的帽绝缘膜和其侧壁上的侧壁膜由氧化硅膜形成。通过CMP方法对形成在栅电极和栅电极之间的多晶硅膜进行抛光，形成接触电极。此外，在逻辑电路区域中的栅电极的侧壁上形成各自由氧化硅膜和多晶硅膜的叠层膜构成的侧壁膜，并且将这些膜用作掩模以形成半导体区域。结果，可以以自对准的方式降低硼渗透并形成接触电极。此外，可以提高构成逻辑电路的MISFET的性能。

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