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1. 发明授权

US10714351B2 Multi-layered substrate manufacturing method 有权
公开(公告)号：US10714351B2
公开(公告)日：2020-07-14
申请号：US13761348
申请日：2013-02-07
申请人： Hidehiro Maeda , Satoshi Katagiri
发明人： Hidehiro Maeda , Satoshi Katagiri
IPC分类号： H01L21/30 , H05K3/00 , H05K3/46 , H05K13/00 , H05K3/38 , H05K3/32 , H01L21/20 , H01L21/683 , H01L21/67 , B32B38/18 , B32B7/12 , B32B37/10
摘要： Provided is a substrate holding unit that holds a pair of substrates that are aligned and layered, comprising a first holding member that holds one of the substrates; a plurality of members to be joined that are connected to the first holding member; a second holding member that holds the other of the substrates to face the one of the substrates; a plurality of joining members that exert an adhesion force on the members to be joined and are connected to the second holding member at positions corresponding to positions of the members to be joined; and an adhesion restricting section that restricts the adhesion force until the substrates are aligned.

2. 发明授权

US09015930B2 Substrate bonding apparatus 有权
标题翻译：基板接合装置
公开(公告)号：US09015930B2
公开(公告)日：2015-04-28
申请号：US12769218
申请日：2010-04-28
申请人： Hidehiro Maeda , Satoshi Katagiri
发明人： Hidehiro Maeda , Satoshi Katagiri
IPC分类号： B23P19/00 , H01L21/30 , H01L21/67
CPC分类号： H01L21/30 , B32B7/12 , B32B37/10 , B32B38/1833 , H01L21/2007 , H01L21/67092 , H01L21/683 , H01L21/6831 , H01L2924/00 , H01L2924/0002 , H05K3/0061 , H05K3/0067 , H05K3/321 , H05K3/325 , H05K3/386 , H05K3/4611 , H05K3/4638 , H05K13/0015 , Y10T29/49126 , Y10T29/4913 , Y10T29/5313 , Y10T29/53196 , Y10T156/10
摘要： Provided is a substrate holding unit that holds a pair of substrates that are aligned and layered, comprising a first holding member that holds one of the substrates; a plurality of members to be joined that are connected to the first holding member; a second holding member that holds the other of the substrates to face the one of the substrates; a plurality of joining members that exert an adhesion force on the members to be joined and are connected to the second holding member at positions corresponding to positions of the members to be joined; and an adhesion restricting section that restricts the adhesion force until the substrates are aligned.
摘要翻译：提供一种基板保持单元，其保持对准且分层的一对基板，包括保持基板之一的第一保持构件; 多个待接合的构件，其连接到第一保持构件; 第二保持构件，其保持另一个基板面对所述一个所述基板; 多个连接构件，其对要接合的构件施加粘合力，并且在对应于待接合构件的位置的位置处连接到第二保持构件; 以及限制直到基板对准的粘合力的粘合限制部。

3. 发明申请

US20130157438A1 SUBSTRATE HOLDING UNIT, SUBSTRATE BONDING APPARATUS, MULTI-LAYERED SUBSTRATE MANUFACTURING APPARATUS, SUBSTRATE BONDING METHOD, MULTI-LAYER SUBSTRATE MANUFACTURING METHOD, AND MULTI-LAYERED SEMICONDUCTOR APPARATUS MANUFACTURING METHOD 审中-公开
标题翻译：基板保持单元，基板接合装置，多层基板制造装置，基板接合方法，多层基板制造方法和多层半导体装置制造方法
公开(公告)号：US20130157438A1
公开(公告)日：2013-06-20
申请号：US13761348
申请日：2013-02-07
申请人： Hidehiro MAEDA , Satoshi Katagiri
发明人： Hidehiro MAEDA , Satoshi Katagiri
IPC分类号： H01L21/30
摘要： Provided is a substrate holding unit that holds a pair of substrates that are aligned and layered, comprising a first holding member that holds one of the substrates; a plurality of members to be joined that are connected to the first holding member; a second holding member that holds the other of the substrates to face the one of the substrates; a plurality of joining members that exert an adhesion force on the members to be joined and are connected to the second holding member at positions corresponding to positions of the members to be joined; and an adhesion restricting section that restricts the adhesion force until the substrates are aligned.
摘要翻译：提供一种基板保持单元，其保持对准且分层的一对基板，包括保持基板之一的第一保持构件; 多个待接合的构件，其连接到第一保持构件; 第二保持构件，其保持另一个基板面对所述一个所述基板; 多个连接构件，其对要接合的构件施加粘合力，并且在对应于待接合构件的位置的位置处连接到第二保持构件; 以及限制直到基板对准的粘合力的粘合限制部。

4. 发明申请

US20100206454A1 SUBSTRATE HOLDING UNIT, SUBSTRATE BONDING APPARATUS, MULTI-LAYERED SUBSTRATE MANUFACTURING APPARATUS, SUBSTRATE BONDING METHOD, MULTI-LAYERED SUBSTRATE MANUFACTURING METHOD, AND MULTI-LAYERED SEMICONDUCTOR APPARATUS MANUFACTURING METHOD 有权
标题翻译：基板保持单元，基板接合装置，多层基板制造装置，基板接合方法，多层基板制造方法和多层半导体装置制造方法
公开(公告)号：US20100206454A1
公开(公告)日：2010-08-19
申请号：US12769218
申请日：2010-04-28
申请人： Hidehiro MAEDA , Satoshi Katagiri
发明人： Hidehiro MAEDA , Satoshi Katagiri
IPC分类号： B29C65/48 , B32B41/00 , B32B37/10
CPC分类号： H01L21/30 , B32B7/12 , B32B37/10 , B32B38/1833 , H01L21/2007 , H01L21/67092 , H01L21/683 , H01L21/6831 , H01L2924/00 , H01L2924/0002 , H05K3/0061 , H05K3/0067 , H05K3/321 , H05K3/325 , H05K3/386 , H05K3/4611 , H05K3/4638 , H05K13/0015 , Y10T29/49126 , Y10T29/4913 , Y10T29/5313 , Y10T29/53196 , Y10T156/10
摘要： Provided is a substrate holding unit that holds a pair of substrates that are aligned and layered, comprising a first holding member that holds one of the substrates; a plurality of members to be joined that are connected to the first holding member; a second holding member that holds the other of the substrates to face the one of the substrates; a plurality of joining members that exert an adhesion force on the members to be joined and are connected to the second holding member at positions corresponding to positions of the members to be joined; and an adhesion restricting section that restricts the adhesion force until the substrates are aligned.
摘要翻译：提供一种基板保持单元，其保持对准且分层的一对基板，包括保持基板之一的第一保持构件; 多个待接合的构件，其连接到第一保持构件; 第二保持构件，其保持另一个基板面对所述一个所述基板; 多个连接构件，其对要接合的构件施加粘合力，并且在对应于待接合构件的位置的位置处连接到第二保持构件; 以及限制直到基板对准的粘合力的粘合限制部。

5. 发明授权

US08072794B2 Semiconductor memory device having DRAM-compatible addressing mode and data processing system including same 有权
标题翻译：具有DRAM兼容寻址模式的半导体存储器件和包括它的数据处理系统
公开(公告)号：US08072794B2
公开(公告)日：2011-12-06
申请号：US12572699
申请日：2009-10-02
申请人： Satoshi Katagiri , Kenji Mae
发明人： Satoshi Katagiri , Kenji Mae
IPC分类号： G11C11/00
CPC分类号： G11C8/12 , G11C7/08 , G11C8/18
摘要： In synchronism with an active command, a row address and a column address are simultaneously received, and a page address is received in synchronism with a read command or a write command. Word drivers select a word line based on the row address, and column switches select a bit line based on the column address. A page address decoder selects any one of read/write amplifiers corresponding to each page based on the page address. With this configuration, a specification for a DRAM such as an access cycle can be satisfied without arranging an amplifier for each bit line, and thus it becomes possible to secure a compatibility with a DRAM while reducing a chip area.
摘要翻译：与活动命令同步，同时接收行地址和列地址，并且与读命令或写命令同步地接收页地址。字驱动程序根据行地址选择字线，列开关根据列地址选择位线。页面地址解码器基于页面地址选择与每个页面相对应的读/写放大器中的任何一个。利用这种配置，可以满足诸如访问周期的DRAM的规范，而不需要为每个位线布置放大器，因此可以在减小芯片面积的同时确保与DRAM的兼容性。

6. 发明授权

US07710790B2 Semiconductor memory device and write control method thereof 失效
标题翻译：半导体存储器件及其写入控制方法
公开(公告)号：US07710790B2
公开(公告)日：2010-05-04
申请号：US12116580
申请日：2008-05-07
申请人： Satoshi Katagiri
发明人： Satoshi Katagiri
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/1072 , G11C7/1096 , G11C7/22 , G11C13/0004 , G11C13/0061
摘要： A semiconductor memory device comprise a word line, a bit line intersecting the word line, a memory element arranged at intersections of the word line and the bit line and having different required time for a write operation according to a logical value of write data, a write driver supplying a write current to the bit line, a write control circuit controlling operations of the write driver, and a timing signal generation circuit supplying a timing signal to the write control circuit. The timing signal has a waveform including a pulse indicating a time of starting supplying the write current when a first logical level is to be written, a pulse indicating a time of ending supplying the write current if the first logical level is to be written, and a pulse indicating one of a time of starting supplying the write current and a time of ending supplying the write current when a second logical level is to be written.
摘要翻译：半导体存储器件包括字线，与字线相交的位线，布置在字线和位线的交点处的存储元件，并且根据写入数据的逻辑值具有不同的写入操作所需的时间，向位线提供写入电流的写入驱动器，控制写入驱动器的操作的写入控制电路以及向写入控制电路提供定时信号的定时信号产生电路。定时信号具有波形，该波形包括当要写入第一逻辑电平时指示开始提供写入电流的时间的脉冲，指示如果要写入第一逻辑电平则提供写入电流的结束时间的脉冲;以及指示在写入第二逻辑电平时开始提供写入电流的时间中的一个和结束提供写入电流的时间的脉冲。

7. 发明申请

US20090010049A1 Phase change memory device 失效
标题翻译：相变存储器件
公开(公告)号：US20090010049A1
公开(公告)日：2009-01-08
申请号：US12216271
申请日：2008-07-02
申请人： Satoshi Katagiri
发明人： Satoshi Katagiri
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0023 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2013/0078
摘要： A phase change memory device is constituted of a plurality of memory cells including a plurality of phase change memory elements, which are arranged at intersecting points formed between a plurality of word lines and a plurality of bit lines. A write circuit which operates based on a write voltage source (Vwrite) is controlled by control signals (e.g. WE, RDIS, SDIS, and DIN) output from a control circuit which operates based on a voltage source (VDD), where Vwrite>VDD. All the control signals based on VDD are applied to the gates of N-channel MOS transistors included in the write circuit. This allows adequately high write currents to be supplied to phase change memory elements; and this eliminates the necessity of arranging a potential switch circuit in the write circuit, thus reducing the scale of the phase change memory device.
摘要翻译：相变存储器件由包括多个相变存储元件的多个存储单元组成，它们被布置在形成在多个字线和多个位线之间的相交点处。基于写入电压源（Vwrite）工作的写入电路由从基于电压源（VDD）工作的控制电路输出的控制信号（例如WE，RDIS，SDIS和DIN）控制，其中Vwrite> VDD 。基于VDD的所有控制信号被施加到写入电路中包括的N沟道MOS晶体管的栅极。这允许向相变存储器元件提供足够高的写入电流; 并且这消除了在写入电路中布置潜在的开关电路的必要性，从而减小了相变存储器件的规模。

8. 发明授权

US06400601B1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06400601B1
公开(公告)日：2002-06-04
申请号：US09602178
申请日：2000-06-22
申请人： Naoaki Sudo , Satoshi Katagiri
发明人： Naoaki Sudo , Satoshi Katagiri
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C16/3454 , G11C2211/5621
摘要： A nonvolatile semiconductor device is provided, which does not need excessive writing or verification operations, except for the originally required writing and verification operations. The data is arranged in the order from the lowest “11”, “10”, “01”, to the highest “01”. Four valued writing data are set in the latches 1 and 2 by data signals DL1 and DL2, and the latch 3 is initialized to “0”. Writing is executed by three stages, and before writing at each stage, if the latch 3 is “0”, the data is transferred to the latch 2. Writing is only executed when any one latch is “0”, and the latch is changed to “1” after the verification is completed. First, writing is executed up to the threshold value of the data “01”, except the data “11” where the latch 2 is “0”. Next, writing is executed for the data “00” and “01” up to the threshold value of the data “00”, where the latch 1 is “0”. Finally, the data “01” where the latch 2 is “0” is written up to the threshold value of “01”.
摘要翻译：提供了不需要过多的写入或验证操作的非易失性半导体器件，除了最初要求的写入和验证操作。数据按照从最低“11”，“10”，“01”到最高“01”的顺序排列。通过数据信号DL1和DL2在锁存器1和2中设置四值写入数据，并且锁存器3被初始化为“0”。写入由三个阶段执行，并且在每个阶段写入之前，如果锁存器3为“0”，则数据被传送到锁存器2.写入仅在任何一个锁存器为“0”且锁存器被改变时才执行到验证完成后为“1”。首先，除了锁存器2为“0”的数据“11”之外，执行直到数据“01”的阈值的写入。接下来，对数据“00”和“01”执行写入，直到数据“00”的阈值为止，其中锁存器1为“0”。最后，将锁存器2为“0”的数据“01”写入阈值“01”。

9. 发明授权

US08264871B2 Phase change memory device 失效
标题翻译：相变存储器件
公开(公告)号：US08264871B2
公开(公告)日：2012-09-11
申请号：US12216271
申请日：2008-07-02
申请人： Satoshi Katagiri
发明人： Satoshi Katagiri
IPC分类号： G11C11/00
CPC分类号： G11C13/0023 , G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2013/0078
摘要： A phase change memory device is constituted of a plurality of memory cells including a plurality of phase change memory elements, which are arranged at intersecting points formed between a plurality of word lines and a plurality of bit lines. A write circuit which operates based on a write voltage source (Vwrite) is controlled by control signals (e.g. WE, RDIS, SDIS, and DIN) output from a control circuit which operates based on a voltage source (VDD), where Vwrite>VDD. All the control signals based on VDD are applied to the gates of N-channel MOS transistors included in the write circuit. This allows adequately high write currents to be supplied to phase change memory elements; and this eliminates the necessity of arranging a potential switch circuit in the write circuit, thus reducing the scale of the phase change memory device.
摘要翻译：相变存储器件由包括多个相变存储元件的多个存储单元组成，它们被布置在形成在多个字线和多个位线之间的相交点处。基于写入电压源（Vwrite）工作的写入电路由从基于电压源（VDD）工作的控制电路输出的控制信号（例如WE，RDIS，SDIS和DIN）控制，其中Vwrite> VDD 。基于VDD的所有控制信号被施加到写入电路中包括的N沟道MOS晶体管的栅极。这允许向相变存储器元件提供足够高的写入电流; 并且这消除了在写入电路中布置潜在的开关电路的必要性，从而减小了相变存储器件的规模。

10. 发明授权

US08050124B2 Semiconductor memory device and method with two sense amplifiers 失效
标题翻译：具有两个读出放大器的半导体存储器件和方法
公开(公告)号：US08050124B2
公开(公告)日：2011-11-01
申请号：US12053395
申请日：2008-03-21
申请人： Yasuko Tonomura , Satoshi Katagiri , Yukio Fuji
发明人： Yasuko Tonomura , Satoshi Katagiri , Yukio Fuji
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/1042 , G11C11/005 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA1) and (SA2) connected to these transfer lines, respectively; and a control circuit making the sense amplifier (SA2) perform a converting operation during an amplifying operation performed by the sense amplifier (SA1). Because the plural sense amplifiers are allocated to the same bit lines, and these are operated in parallel in this way, data can be read at a high speed.
摘要翻译：半导体存储器件包括：分别与多个存储单元相连的多个位线; 多个传输线共同分配给多个位线; 感测放大器（SA1）和（SA2）分别连接到这些传输线; 以及使读出放大器（SA2）在由读出放大器（SA1）执行的放大操作期间执行转换操作的控制电路。因为将多个读出放大器分配给相同的位线，并且这些以这种方式并行操作，所以可以高速读取数据。

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