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1. 发明申请

US20080247227A1 SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF 失效
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20080247227A1
公开(公告)日：2008-10-09
申请号：US12053395
申请日：2008-03-21
申请人： Yasuko TONOMURA , Satoshi KATAGIRI , Yukio Fuji
发明人： Yasuko TONOMURA , Satoshi KATAGIRI , Yukio Fuji
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/08 , G11C7/1042 , G11C11/005 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA1) and (SA2) connected to these transfer lines, respectively; and a control circuit making the sense amplifier (SA2) perform a converting operation during an amplifying operation performed by the sense amplifier (SA1). Because the plural sense amplifiers are allocated to the same bit lines, and these are operated in parallel in this way, data can be read at a high speed.
摘要翻译：半导体存储器件包括：分别与多个存储单元相连的多个位线; 多个传输线共同分配给多个位线; 读取放大器（SA 1）和（SA 2）分别连接到这些传输线; 以及使读出放大器（SA2）在由读出放大器（SA 1）执行的放大操作期间执行转换操作的控制电路。因为将多个读出放大器分配给相同的位线，并且这些以这种方式并行操作，所以可以高速读取数据。

2. 发明授权

US08050124B2 Semiconductor memory device and method with two sense amplifiers 失效
标题翻译：具有两个读出放大器的半导体存储器件和方法
公开(公告)号：US08050124B2
公开(公告)日：2011-11-01
申请号：US12053395
申请日：2008-03-21
申请人： Yasuko Tonomura , Satoshi Katagiri , Yukio Fuji
发明人： Yasuko Tonomura , Satoshi Katagiri , Yukio Fuji
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/1042 , G11C11/005 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA1) and (SA2) connected to these transfer lines, respectively; and a control circuit making the sense amplifier (SA2) perform a converting operation during an amplifying operation performed by the sense amplifier (SA1). Because the plural sense amplifiers are allocated to the same bit lines, and these are operated in parallel in this way, data can be read at a high speed.
摘要翻译：半导体存储器件包括：分别与多个存储单元相连的多个位线; 多个传输线共同分配给多个位线; 感测放大器（SA1）和（SA2）分别连接到这些传输线; 以及使读出放大器（SA2）在由读出放大器（SA1）执行的放大操作期间执行转换操作的控制电路。因为将多个读出放大器分配给相同的位线，并且这些以这种方式并行操作，所以可以高速读取数据。

3. 发明授权

US07692979B2 Memory readout circuit and phase-change memory device 失效
标题翻译：存储器读出电路和相变存储器件
公开(公告)号：US07692979B2
公开(公告)日：2010-04-06
申请号：US11943608
申请日：2007-11-21
申请人： Yukio Fuji , Yasuko Tonomura
发明人： Yukio Fuji , Yasuko Tonomura
IPC分类号： G11C7/22
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/0052 , G11C2013/0054 , G11C2013/0092
摘要： In a memory readout circuit for use in a phase-change memory device comprising phase-change elements as memory cells, a sense amplifier sets readout voltage, which is applied to a selected phase-change element selected among the phase-change elements by a column selecting switch, to voltage equal to or higher than hold voltage of the selected phase-change element but lower than transition voltage of the selected phase-change element in a readout cycle. The selected phase-change element is read out as a dynamic state in the case where the selected phase-change element is in a set state.
摘要翻译：在用于包括相变元件作为存储单元的相变存储器件中的存储器读出电路中，读出放大器设置读出电压，该读出电压施加到通过一列的相变元件中选择的所选择的相变元件选择开关至等于或高于所选择的相变元件的保持电压但低于读出周期中所选择的相变元件的转换电压的电压。在选择的相变元件处于设定状态的情况下，所选择的相变元件被读出为动态。

4. 发明申请

US20080117669A1 MEMORY READOUT CIRCUIT AND PHASE-CHANGE MEMORY DEVICE 失效
标题翻译：存储器读出电路和相变存储器件
公开(公告)号：US20080117669A1
公开(公告)日：2008-05-22
申请号：US11943608
申请日：2007-11-21
申请人： Yukio Fuji , Yasuko Tonomura
发明人： Yukio Fuji , Yasuko Tonomura
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/0052 , G11C2013/0054 , G11C2013/0092
摘要： In a memory readout circuit for use in a phase-change memory device comprising phase-change elements as memory cells, a sense amplifier sets readout voltage, which is applied to a selected phase-change element selected among the phase-change elements by a column selecting switch, to voltage equal to or higher than hold voltage of the selected phase-change element but lower than transition voltage of the selected phase-change element in a readout cycle. The selected phase-change element is read out as a dynamic state in the case where the selected phase-change element is in a set state.
摘要翻译：在用于包括相变元件作为存储单元的相变存储器件中的存储器读出电路中，读出放大器设置读出电压，该读出电压施加到通过一列的相变元件中选择的所选择的相变元件选择开关至等于或高于所选择的相变元件的保持电压但低于读出周期中所选择的相变元件的转换电压的电压。在选择的相变元件处于设定状态的情况下，所选择的相变元件被读出为动态。

5. 发明授权

US07646633B2 Method for programming phase-change memory and method for reading date from the same 失效
标题翻译：编程相变存储器的方法和从其读取日期的方法
公开(公告)号：US07646633B2
公开(公告)日：2010-01-12
申请号：US12038547
申请日：2008-02-27
申请人： Yukio Fuji
发明人： Yukio Fuji
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/79
摘要： When a phase-change element that can transition between a reset state (amorphous state) and a set state (crystalline state) is to be caused to transition to the reset state, a first pulse having a first voltage is applied to the phase-change element. The first voltage is higher than the threshold voltage in the reset state, and can cause current to flow that corresponds to an amount of generated heat required for placing the element in the reset state. When the phase-change element is to be caused to transition to the set state, a second pulse having a second voltage and the same time width as the first pulse is applied to the phase-change element. The second voltage that is higher than the threshold voltage but lower than the first voltage, and can cause only a current to flow that does not attain the necessary amount of generated heat.
摘要翻译：当要使复位状态（非晶状态）和设定状态（结晶状态）之间转换的相变元件转变到复位状态时，具有第一电压的第一脉冲被施加到相变元件。第一电压高于复位状态下的阈值电压，并且可导致电流流动，其对应于将元件置于复位状态所需的发热量。当相变元件转变到设定状态时，具有与第一脉冲相同的第二电压和时间宽度的第二脉冲施加到相变元件。第二电压高于阈值电压但低于第一电压，并且只能导致不达到所需量的产生的热量的电流。

6. 发明授权

US07580277B2 Memory device including a programmable resistance element 有权
标题翻译：存储器件包括可编程电阻元件
公开(公告)号：US07580277B2
公开(公告)日：2009-08-25
申请号：US12207077
申请日：2008-09-09
申请人： Yukio Fuji
发明人： Yukio Fuji
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/406 , G11C11/4099 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0064 , G11C16/3431 , G11C16/349 , G11C2211/4061
摘要： Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.
摘要翻译：公开了一种具有改进的相变装置的保持特性的相变存储器，以及用于刷新相变存储器的方法。存储器是DRAM接口兼容存储器的事实被利用。根据读写操作的次数提供了被压制的虚拟单元。比较电路检测虚设电池的电阻值的变化。如果电阻值已经改变超过预定参考值（即，改变为低电阻），则刷新请求电路请求未示出的内部电路实现刷新。存储器单元和虚拟单元被过饱和刷新，并且对相变装置的编程电阻值的变化进行校正，以确保余量以及改善保持特性。

7. 发明申请

US20080043522A1 Nonvolatile Semiconductor Memory Device and Phase Change Memory Device 有权
标题翻译：非易失性半导体存储器件和相变存储器件
公开(公告)号：US20080043522A1
公开(公告)日：2008-02-21
申请号：US11666160
申请日：2005-10-25
申请人： Yukio Fuji , Isamu Asano , Tsuyoshi Kawagoe , Kiyoshi Nakai
发明人： Yukio Fuji , Isamu Asano , Tsuyoshi Kawagoe , Kiyoshi Nakai
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C2213/78 , H01L27/0207 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.
摘要翻译：为了通过获得用于高集成相变存储器件的足够的写入电流来提供有利于布局和操作控制的相变存储器件，本发明的非易失性半导体存储器件，其中字线和位线被布置成矩阵型，形状包括形成在字线和位线的每个交叉点处的选择晶体管，以及多个存储元件，其一端共同连接到选择晶体管，并且在另一端连接到不同的元件选择线，并且能够写和读数据。通过提供预定电流通过选择晶体管并通过连接到所选择的存储元件的元件选择线来控制所选存储元件的写和读操作，并且元件选择线与位线并联布置。

8. 发明申请

US20060294034A1 Artificial neural network 失效
公开(公告)号：US20060294034A1
公开(公告)日：2006-12-28
申请号：US11473127
申请日：2006-06-23
申请人： Yukio Fuji
发明人： Yukio Fuji
IPC分类号： G06N3/00 , G06F15/18 , G06J1/00
CPC分类号： G06N3/063
摘要： An artificial neural network that can act like the real neural network according to the input history of signals input. The network includes a learning circuit that stores an input history of an input signal, an output circuit that is connected to the learning circuit, and a reset circuit that resets the input history stored in the learning circuit. The learning circuit changes a potential-change characteristic of an internal node included in the output circuit, according to the input history. The output circuit starts an output operation of data when a potential at the internal node exceeds a threshold value. The artificial neural network of this invention can operate almost in the same way as the real neural network, because it performs an output operation, such as an oscillating operation, in response to the history of the input signal.

9. 发明申请

US20060190672A1 Semiconductor memory device and writing method thereof 失效
标题翻译：半导体存储器件及其写入方法
公开(公告)号：US20060190672A1
公开(公告)日：2006-08-24
申请号：US11340623
申请日：2006-01-27
申请人： Yukio Fuji
发明人： Yukio Fuji
IPC分类号： G06F12/00 , G06F12/14 , G06F13/28 , G06F12/16 , G06F13/00
CPC分类号： G11C13/0069 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C13/0004 , G11C13/004 , G11C2013/0076
摘要： To provide a semiconductor memory device comprising a phase-change memory and having high compatibility with DRAM interface. The memory cell array 18 comprises a memory cell that includes a phase-change element provided at the intersection of a bit line and word line. A write address and data accompanying a write request are temporarily held in a write address register 15 and a data register 14 respectively, and a write operation is not performed on the memory cell array 18 in this cycle of write request. And when a next write request occurs, the held data is written to the memory cell array 18. At this time, two write cycles—RESET cycle and SET cycle—are provided. Then the written contents of the memory cell and the rewrite data are compared, and after only SET cells are temporarily RESET (amorphization, increasing the resistance), it is operated so as to write only SET data (crystallization, lowering the resistance).
摘要翻译：提供包括相变存储器并且与DRAM接口具有高兼容性的半导体存储器件。存储单元阵列18包括存储单元，其包括设置在位线和字线的交点处的相变单元。写入地址和与写入请求相关的数据分别临时保存在写入地址寄存器15和数据寄存器14中，并且在写入请求循环中不对存储单元阵列18进行写入操作。并且当发生下一个写入请求时，保持的数据被写入存储单元阵列18。此时，提供两个写周期 - 复位周期和SET周期。然后比较存储单元的写入内容和重写数据，只有SET单元暂时复位（非晶化，增加电阻）之后，才能操作SET数据（结晶，降低电阻）。

10. 发明授权

US07646626B2 Page mode access for non-volatile memory arrays 有权
标题翻译：非易失性存储器阵列的页面模式访问
公开(公告)号：US07646626B2
公开(公告)日：2010-01-12
申请号：US12074274
申请日：2008-03-03
申请人： Ward Parkinson , Yukio Fuji
发明人： Ward Parkinson , Yukio Fuji
IPC分类号： G11C11/00
CPC分类号： G11C7/1021 , G11C7/065 , G11C7/08 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C7/22 , G11C13/0004 , G11C13/0026 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C16/3431 , G11C2013/0085 , G11C2207/005
摘要： An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.
摘要翻译：布置在逻辑列和逻辑行中的非易失性存储器单元的阵列，以及相关联的电路，以使得能够并行地读取或写入行上的一个或多个存储器单元。在一些实施例中，存储器单元阵列可以包括相变材料。在一些实施例中，电路可以包括写入驱动器，读取驱动器，读出放大器以及通过扩展刷新来将存储器单元与读出放大器隔离的电路。

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