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1. 发明授权

US07303964B2 Self-aligned STI SONOS 有权
标题翻译：自对准STI SONOS
公开(公告)号：US07303964B2
公开(公告)日：2007-12-04
申请号：US11113509
申请日：2005-04-25
申请人： Hidehiko Shiraiwa , Mark Randolph , Yu Sun
发明人： Hidehiko Shiraiwa , Mark Randolph , Yu Sun
IPC分类号： H01L21/336
CPC分类号： H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573
摘要： Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a multi-layer dielectric-charge trapping-dielectric stack 420 over a substrate 408 of the wafer 402, for example, an ONO stack 420, removing 312 the multi-layer dielectric-charge trapping-dielectric stack 420 in a periphery region 406 of the wafer 402, thereby defining a multi-layer dielectric-charge trapping-dielectric stack 420 in a core region 404 of the wafer 402. The method 300 further comprises forming 314 a gate dielectric layer 426 over the periphery region 406 of the substrate 408, forming 316 a first polysilicon layer 428 over the multi-layer dielectric-charge trapping-dielectric stack 420 in the core region 402 and the gate dielectric 426 in the periphery region 406 , then concurrently forming 318 an isolation trench 438 in the substrate 408 in the core region 404 and in the periphery region 406. Thereafter, the isolation trenches are filled 326 with a dielectric material 446, and a second polysilicon layer 452 that is formed 332 over the first polysilicon layer 428 and the filled trenches 438, forming an self-aligned STI structure 446. The method 300 avoids ONO residual stringers at STI edges in the periphery region, reduces active region losses, reduces thinning of the periphery gate oxide and the ONO at the STI edge, and reduces dopant diffusion during isolation implantations due to reduced thermal process steps.
摘要翻译：公开了用于在多位SONOS闪存器件中制造浅隔离沟槽和结构的方法300和350。一个方法方面300包括在晶片402的衬底408（例如，ONO堆叠420）上形成310多层介电电荷俘获 - 电介质堆叠420，去除312多层介电电荷俘获 - 电介质堆叠420 在晶片402的外围区域406中，由此在晶片402的芯区域404中限定多层介电电荷捕获 - 电介质叠层420。方法300还包括在衬底408的外围区域406上形成314栅极电介质层426，在芯区域402中的多层介电电荷捕获 - 电介质堆叠层420上形成316第一多晶硅层428，并且栅极在外围区域406中的电介质426，然后同时在芯区域404和周边区域406中的衬底408中形成318隔离沟槽438。此后，绝缘沟槽用介电材料446填充326，第二多晶硅层452在第一多晶硅层428和填充沟槽438上形成332，形成自对准STI结构446。方法300避免在外围区域的STI边缘处的ONO残余桁条，减少有源区域损耗，减少STI边缘处的外围栅极氧化物和ONO的稀化，并且由于减少的热处理步骤，在隔离注入期间减少掺杂剂扩散。

2. 发明申请

US20060240635A1 Self-aligned STI SONOS 有权
标题翻译：自对准STI SONOS
公开(公告)号：US20060240635A1
公开(公告)日：2006-10-26
申请号：US11113509
申请日：2005-04-25
申请人： Hidehiko Shiraiwa , Mark Randolph , Yu Sun
发明人： Hidehiko Shiraiwa , Mark Randolph , Yu Sun
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573
摘要： Methods 300 and 350 are disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspect 300 comprises forming 310 a multi-layer dielectric-charge trapping-dielectric stack 420 over a substrate 408 of the wafer 402, for example, an ONO stack 420, removing 312 the multi-layer dielectric-charge trapping-dielectric stack 420 in a periphery region 406 of the wafer 402, thereby defining a multi-layer dielectric-charge trapping-dielectric stack 420 in a core region 404 of the wafer 402. The method 300 further comprises forming 314 a gate dielectric layer 426 over the periphery region 406 of the substrate 408, forming 316 a first polysilicon layer 428 over the multi-layer dielectric-charge trapping-dielectric stack 420 in the core region 402 and the gate dielectric 426 in the periphery region 406 , then concurrently forming 318 an isolation trench 438 in the substrate 408 in the core region 404 and in the periphery region 406. Thereafter, the isolation trenches are filled 326 with a dielectric material 446, and a second polysilicon layer 452 that is formed 332 over the first polysilicon layer 428 and the filled trenches 438, forming an self-aligned STI structure 446. The method 300 avoids ONO residual stringers at STI edges in the periphery region, reduces active region losses, reduces thinning of the periphery gate oxide and the ONO at the STI edge, and reduces dopant diffusion during isolation implantations due to reduced thermal process steps.
摘要翻译：公开了用于在多位SONOS闪存器件中制造浅隔离沟槽和结构的方法300和350。一个方法方面300包括在晶片402的衬底408（例如，ONO堆叠420）上形成310多层介电电荷俘获 - 电介质堆叠420，去除312多层介电电荷俘获 - 电介质堆叠420 在晶片402的外围区域406中，由此在晶片402的芯区域404中限定多层介电电荷捕获 - 电介质叠层420.方法300还包括在周边区域314上形成314栅极电介质层426 406，在芯区域402中的多层介电 - 电荷俘获 - 电介质堆叠层420和周边区域406中的栅极电介质426之间形成316第一多晶硅层428，然后同时形成318隔离沟槽438 在核心区域404和外围区域406中的衬底408中。此后，隔离沟槽用介电材料446填充326，第二多晶硅层452形成为332o 形成第一多晶硅层428和填充沟槽438，形成自对准STI结构446.方法300避免在外围区域的STI边缘处的ONO残余桁条，减少有源区域损耗，减少外围栅极氧化物的稀化和 ONO在STI边缘，并且由于减少的热处理步骤，在隔离注入期间减少掺杂剂扩散。

3. 发明授权

US06730564B1 Salicided gate for virtual ground arrays 有权
标题翻译：用于虚拟地面阵列的闸门
公开(公告)号：US06730564B1
公开(公告)日：2004-05-04
申请号：US10217821
申请日：2002-08-12
申请人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
发明人： Mark T. Ramsbey , Yu Sun , Chi Chang , Hidehiko Shiraiwa
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , Y10S438/954
摘要： The present invention provides a process for saliciding word lines in a virtual ground array flash memory device without causing shorting between bit lines. According to one aspect of the invention, saliciding takes place prior to patterning one or more layers of a memory cell stack. The unpatterned layers protect the substrate between word lines from becoming salicided. The invention provides virtual ground array flash memory devices with doped and salicided word lines, but no shorting between bit lines, even in virtual ground arrays where there are no oxide island isolation regions between word lines. Potential advantages of such structures include reduced size, reduced number of processing steps, and reduced exposure to high temperature cycling.
摘要翻译：本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不引起位线之间的短路。根据本发明的一个方面，在对存储单元堆叠的一层或多层进行构图之前进行水化。未图案化的层保护字线之间的基板不会变成水银。本发明提供具有掺杂和含水字线的虚拟接地阵列闪存器件，但是即使在字线之间没有氧化物岛隔离区域的虚拟接地阵列中也不会在位线之间发生短路。这种结构的潜在优点包括减小的尺寸，减少的加工步骤数量以及降低暴露于高温循环。

4. 发明授权

US08673716B2 Memory manufacturing process with bitline isolation 有权
标题翻译：内存制造过程采用位线隔离
公开(公告)号：US08673716B2
公开(公告)日：2014-03-18
申请号：US10118732
申请日：2002-04-08
申请人： Mark T. Ramsbey , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Yu Sun
发明人： Mark T. Ramsbey , Tazrien Kamal , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Yu Sun
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.
摘要翻译：集成电路的制造方法具有具有芯区域和周边区域的半导体基板。在芯区域中沉积电荷捕获电介质层，并且在周边区域中沉积栅极电介质层。位线在芯区域中的半导体衬底中而不是在周边区域中形成。在芯区域而不是周边区域中形成并注入掺杂剂的字线栅层。形成了一条字和门。源极/漏极结在栅极周围的半导体衬底中注入掺杂剂，栅极注入栅极掺杂注入在外围区域而不在核心区域。

5. 发明授权

US06900085B2 ESD implant following spacer deposition 有权
标题翻译：间隔物沉积后的ESD植入
公开(公告)号：US06900085B2
公开(公告)日：2005-05-31
申请号：US09891885
申请日：2001-06-26
申请人： Mark T. Ramsbey , Michael Fliesler , Mark Randolph , Mimi Qian , Yu Sun
发明人： Mark T. Ramsbey , Michael Fliesler , Mark Randolph , Mimi Qian , Yu Sun
IPC分类号： H01L27/02 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/7833 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.
摘要翻译：本发明的一个方面提供了一种用于形成具有ESD保护晶体管的IC器件的方法。根据本发明的一个方面，ESD保护晶体管具有轻掺杂，然后在形成间隔物之后，进行重掺杂。具有间隔物的重掺杂可以降低薄层电阻，增强晶体管的双极效应，降低晶体管的电容，并降低结击穿电压，而不会导致短沟道效应。因此，本发明提供了紧凑，高灵敏度和快速切换的ESD保护晶体管。间隔物可以与其他晶体管的间隔物同时形成，例如器件的外围区域中的其它晶体管。

6. 发明授权

US06444530B1 Process for fabricating an integrated circuit with a self-aligned contact 有权
标题翻译：用于制造具有自对准接触的集成电路的工艺
公开(公告)号：US06444530B1
公开(公告)日：2002-09-03
申请号：US09318429
申请日：1999-05-25
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/76897 , H01L23/485 , H01L27/115 , H01L2924/0002 , Y10T428/12542 , Y10T428/1259 , Y10T428/12625 , Y10T428/12778 , H01L2924/00
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.
摘要翻译：在闪速存储器件中形成触点的方法利用局部互连处理技术。局部互连处理技术允许接触件与存储器单元相关联的堆叠栅极对接或重叠。接触可以包括钨。堆叠的栅极被也覆盖绝缘间隔物的阻挡层覆盖。

7. 发明授权

US5907781A Process for fabricating an integrated circuit with a self-aligned contact 失效
公开(公告)号：US5907781A
公开(公告)日：1999-05-25
申请号：US49517
申请日：1998-03-27
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L21/335
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

8. 发明授权

US10789543B1 Functional object-oriented networks for manipulation learning 有权
公开(公告)号：US10789543B1
公开(公告)日：2020-09-29
申请号：US14922531
申请日：2015-10-26
申请人： Yu Sun
发明人： Yu Sun
IPC分类号： G06N5/02 , G06N20/00 , G06N7/00 , B25J9/16
摘要： In some embodiments, a functional object-oriented network (FOON) is provided that includes a plurality of functional units each comprising two or more input object nodes that each identify an object and its state before a manipulation motion is performed, a motion node that identifies a manipulation motion that can be performed using the objects, and one or more output object nodes that each identify an object and its state after the manipulation motion has been performed using the objects. In some embodiment, a robot can used the FOON to determine the discrete actions that are required to perform a given task.

9. 发明申请

US20200255637A1 METHOD AND PRODUCT OF MODIFYING VULCANIZED RUBBER 审中-公开
公开(公告)号：US20200255637A1
公开(公告)日：2020-08-13
申请号：US16787716
申请日：2020-02-11
申请人： Georg Bohm , Xuesong Yan , Yu Sun , Li Jia
发明人： Georg Bohm , Xuesong Yan , Yu Sun , Li Jia
IPC分类号： C08L17/00 , C08C19/08
摘要： A method, and product thereof, for modifying the surface of recycled sulfur-cured rubber via surface devulcanization that minimizes alteration of the network structure of the recycled sulfur-cured rubber, while generating strong tack between mixed recycled rubber and fresh rubber for optimal adhesion upon subsequent co-curing. In one embodiment, the surface of recycled rubber is devulcanized by treating recycled rubber with a thiol and a base dissolved in a solvent that does not effectively penetrate and only minimally swells vulcanized rubbers.

10. 发明申请

US20200040165A1 ACTIVATED ISOBUTYLENE-ISOPRENE RUBBER AND THERMOSET RUBBER THEREFROM 审中-公开
公开(公告)号：US20200040165A1
公开(公告)日：2020-02-06
申请号：US16053048
申请日：2018-08-02
申请人： Li JIA , Yu Sun , Mara Kuenen
发明人： Li JIA , Yu Sun , Mara Kuenen
IPC分类号： C08L9/00 , C08C19/28
摘要： In one or more embodiments, the present invention provides an way to modify the isoprene unit using an alder-ene reaction to form thermoset compounds comprising the resultant electron-deficient, readily crosslinkable polyisobutylene-based rubber that avoids the use of corrosive bromine or chlorine to make the activated butyl rubber, is easier to crosslink than the halobutyls, allows crosslinking with a simple organic base or a peroxide, and has mechanical properties as good as or better than sulfur crosslinked butyl rubbers.

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