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1. 发明授权

US5854562A Sense amplifier circuit 失效
标题翻译：感应放大电路
公开(公告)号：US5854562A
公开(公告)日：1998-12-29
申请号：US842536
申请日：1997-04-15
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C11/419 , G11C7/06 , G11C11/409
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译：一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以减少输出响应的延迟时间。

2. 发明授权

US06271687B1 Sense amplifier circuit 有权
标题翻译：感应放大电路
公开(公告)号：US06271687B1
公开(公告)日：2001-08-07
申请号：US09531530
申请日：2000-03-21
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C706
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on a small voltage difference of input signals being amplified in two stages and the amplifying circuit being 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译：一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以减少输出响应的延迟时间。

3. 发明授权

US06046609A Sense amplifier circuit 有权
标题翻译：感应放大电路
公开(公告)号：US06046609A
公开(公告)日：2000-04-04
申请号：US188369
申请日：1998-11-10
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C11/419 , G11C7/06 , G11C11/409
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译：一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以降低输出响应的延迟时间。

4. 发明授权

US5963483A Synchronous memory unit 失效
标题翻译：同步存储单元
公开(公告)号：US5963483A
公开(公告)日：1999-10-05
申请号：US133952
申请日：1998-08-14
申请人： Hideharu Yahata , Kenichi Fukui , Yoji Nishio , Atsushi Hiraishi , Sadayuki Morita
发明人： Hideharu Yahata , Kenichi Fukui , Yoji Nishio , Atsushi Hiraishi , Sadayuki Morita
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the input latches, and a memory cell array having a plurality of memory cells which store and output data signals via bit lines according to the address data decoded by the decoders. Also provided are a sense amplifier for amplifying the output data signals on the bit lines, a selector for selecting one of the amplified output data signals according to the address data decoded by the decoders, and a selector output latch for holding and outputting the amplified output data signal from the selector according to the clock signal. An output latch holds and outputs the amplified output data signal from the selector output latch according to the clock signal. An output buffer receives and outputs the amplified output data signal from the output latch. Each latch includes a first latch for holding and outputting a data signal according to the clock signal, a first switch connected to the first latch for allowing a data signal to pass to the first latch according to the clock signal, and a second latch for holding and outputting a data signal according to the clock signal, and a second switch, connected between the first and second latches, for allowing a data signal to pass from the first latch to the second latch according to the clock signal.
摘要翻译：一种同步存储单元，包括用于接收地址数据的多个输入缓冲器，用于根据时钟信号从输入缓冲器中保存和输出地址数据的多个输入锁存器，用于从输入端解码地址数据的多个解码器锁存器和具有多个存储器单元的存储单元阵列，存储单元根据解码器解码的地址数据经由位线存储和输出数据信号。还提供了用于放大位线上的输出数据信号的读出放大器，用于根据由解码器解码的地址数据来选择放大的输出数据信号之一的选择器，以及用于保存并输出放大的输出的选择器输出锁存器来自选择器的数据信号根据时钟信号。输出锁存器根据时钟信号保存并输出来自选择器输出锁存器的放大输出数据信号。输出缓冲器从输出锁存器接收并输出放大的输出数据信号。每个锁存器包括用于根据时钟信号保持和输出数据信号的第一锁存器，连接到第一锁存器的第一开关，用于根据时钟信号使数据信号传送到第一锁存器;以及第二锁存器，用于保持并根据时钟信号输出数据信号，以及连接在第一和第二锁存器之间的第二开关，用于根据时钟信号允许数据信号从第一锁存器传递到第二锁存器。

5. 发明授权

US5936909A Static random access memory 失效
标题翻译：静态随机存取存储器
公开(公告)号：US5936909A
公开(公告)日：1999-08-10
申请号：US13911
申请日：1998-01-27
申请人： Takahiro Sonoda , Sadayuki Morita , Hirofumi Zushi , Haruko Kawachino , Hideharu Yahata , Kenichi Fukui , Tomohiro Nagano , Masashige Harada
发明人： Takahiro Sonoda , Sadayuki Morita , Hirofumi Zushi , Haruko Kawachino , Hideharu Yahata , Kenichi Fukui , Tomohiro Nagano , Masashige Harada
IPC分类号： G11C7/10 , G11C11/418 , G11C7/00
CPC分类号： G11C7/1072 , G11C11/418 , G11C7/1018
摘要： A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address selection circuit selects a memory cell in one of the memory mats, and connects the selected memory cell to a sense amplifier or a write amplifier furnished corresponding to the memory mat in question. At the same time, an address counter generates an address signal corresponding to the address signal by which one of the memory mats has been selected. When a burst mode is designated by a control signal, the address signal admitted to the address register is used to select a memory cell in a first memory mat. The selected memory cell is connected to the corresponding sense amplifier or write amplifier. Then in accordance with the address signal generated by the address counter, a memory cell in another memory mat is selected and connected to the corresponding sense amplifier or write amplifier.
摘要翻译：静态RAM具有多个存储器堆，每个存储器堆包括在多个字线和多个数据线之间的交点处以矩阵模式形成的多个静态存储器单元。地址选择电路在接收到地址寄存器中的地址信号后，选择存储器垫之一中的存储单元，并将所选择的存储单元连接到与所讨论的存储器衬垫对应的读出放大器或写入放大器。同时，地址计数器产生与已经选择了一个存储器垫的地址信号对应的地址信号。当通过控制信号指定突发模式时，允许进入地址寄存器的地址信号用于选择第一存储器存储器中的存储器单元。所选择的存储单元连接到相应的读出放大器或写放大器。然后根据地址计数器产生的地址信号，选择另一个存储器存储器中的存储单元并将其连接到相应的读出放大器或写入放大器。

6. 发明授权

US06274895B1 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06274895B1
公开(公告)日：2001-08-14
申请号：US09385631
申请日：1999-08-27
申请人： Isamu Fujii , Kiyoshi Nakai , Yukihide Suzuki , Sadayuki Morita , Hidekazu Egawa , Katura Abe , Noriaki Sakamoto
发明人： Isamu Fujii , Kiyoshi Nakai , Yukihide Suzuki , Sadayuki Morita , Hidekazu Egawa , Katura Abe , Noriaki Sakamoto
IPC分类号： H01L2710
CPC分类号： H01L27/10897 , G11C5/025 , G11C11/4097 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.
摘要翻译：具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。在每个单位区域上形成沿第一方向延伸的第一互连。沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。在每个单元区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式，根据需要，根据与其相邻的布线专用区域的组合。

7. 发明授权

US5677887A Semiconductor memory device having a large storage capacity and a high speed operation 失效
标题翻译：具有大存储容量和高速操作的半导体存储器件
公开(公告)号：US5677887A
公开(公告)日：1997-10-14
申请号：US401693
申请日：1995-03-10
申请人： Koichiro Ishibashi , Katsuro Sasaki , Kunihiro Komiyaji , Toshiro Aoto , Sadayuki Morita
发明人： Koichiro Ishibashi , Katsuro Sasaki , Kunihiro Komiyaji , Toshiro Aoto , Sadayuki Morita
IPC分类号： G11C7/06 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/418 , G11C29/00 , G11C29/04 , G11C29/26 , G11C29/38 , H01L21/8244 , H01L27/11 , G11C11/40
CPC分类号： G11C29/70 , G11C11/418 , G11C29/26 , G11C29/38 , G11C29/78 , G11C7/06 , G11C8/14 , Y10S257/903 , Y10S257/904
摘要： A semiconductor static memory device, which has an increased storage capacity without imposing an increased access time, includes first, second and third metallic layers. To begin, word lines for the transfer MOSFETS are formed of the same polysilicon layer used to form the gate electrodes of the transfer MOSFETs of the memory device. A metallic layer of the first layer is used for local word lines, with the polysilicon word lines and local word lines being connected at their ends or inside of cell arrays. A metallic layer of the second layer is used for bit layers, and a metallic layer of the third layer is used for main word lines. Consequently, the word lines have a decreased time constant, allowing fast memory access. Each of sense amplifiers used in the memory device are formed with MOSFETs, which are disposed divisionally in adjacent locations. Preferably the gate electrodes of the divided MOSFETs are located symmetrically. In this case, the offset voltage of the sense amplifiers decreases significantly.
摘要翻译：具有增加的存储容量而不增加访问时间的半导体静态存储器件包括第一，第二和第三金属层。为了开始，转移MOSFET的字线由用于形成存储器件的转移MOSFET的栅电极的相同的多晶硅层形成。第一层的金属层用于本地字线，多晶硅字线和局部字线在其单元阵列的端部或内部连接。第二层的金属层用于位层，第三层的金属层用于主字线。因此，字线具有减小的时间常数，允许快速存储器访问。在存储器件中使用的读出放大器中的每一个都由具有分开设置在相邻位置的MOSFET构成。优选地，分割的MOSFET的栅电极对称地定位。在这种情况下，读出放大器的偏移电压显着降低。

8. 发明授权

US5226583A Module frame work for larger structure, method and device for assembling module frame work and coupler for module frame work 失效
标题翻译：用于组装模块框架工作的大型结构，方法和装置的模块框架和用于模块框架工作的耦合器
公开(公告)号：US5226583A
公开(公告)日：1993-07-13
申请号：US745246
申请日：1991-08-14
申请人： Yoshinori Imashimizu , Yoshiaki Suda , Shuichi Yamamoto , Toshiyuki Takada , Kaoru Maeyama , Etsuro Hiramoto , Toshihide Oki , Sadayuki Morita , Shoji Kawatani , Kunihito Morioka , Ryoichi Fujimitsu , Kazuhisa Handa
发明人： Yoshinori Imashimizu , Yoshiaki Suda , Shuichi Yamamoto , Toshiyuki Takada , Kaoru Maeyama , Etsuro Hiramoto , Toshihide Oki , Sadayuki Morita , Shoji Kawatani , Kunihito Morioka , Ryoichi Fujimitsu , Kazuhisa Handa
IPC分类号： B63B3/00 , B63H21/30
CPC分类号： B63H21/30 , B63B3/00 , Y10T29/49625 , Y10T29/49892 , Y10T29/49963 , Y10T403/50
摘要： A module frame work to which outfits are mounted is manufactured with high accuracy and is installed to a larger structure without adjustment operation. The module frame work comprises a pair of horizontal and mutually parallel main beams, a pair of beam members connecting the main beams, support columns vertically extending from each of junctions of the main beams with the beam members and at least a connector on an end of any of the main beams, beam members and support columns.

9. 发明授权

US06885599B2 Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device 失效
标题翻译：半导体晶片，半导体芯片和半导体器件的制造方法
公开(公告)号：US06885599B2
公开(公告)日：2005-04-26
申请号：US10764539
申请日：2004-01-27
申请人： Yoshikazu Saitoh , Sadayuki Morita , Takahiro Sonoda
发明人： Yoshikazu Saitoh , Sadayuki Morita , Takahiro Sonoda
IPC分类号： G01R31/30 , G01R31/28 , G11C29/00 , G11C29/48 , H01L21/66 , G11C7/00
CPC分类号： G11C29/48
摘要： By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.
摘要翻译：通过在老化期间使用少量的针和接触端子，在每个针与每个半导体芯片中提供的每个端子之间进行电接触检查，从而可以提高组装产品的产量。根据其中形成有易失性存储器芯片和非易失性存储器芯片的封装结构，根据在半导体晶片的状态下执行每个存储芯片的老化的生产方案，并且通过使用经过老化的良好易失性存储器芯片以及类似地，非易失性存储器芯片形成封装结构。在该老化期间，通过将设置在老化板中的针与例如在每个半导体芯片上形成的测试电路的六个测试信号端子接触来进行接触检查。

10. 发明授权

US06707139B2 Semiconductor device with plural unit regions in which one or more MOSFETs are formed 有权
标题翻译：具有多个单位区域的半导体器件，其中形成有一个或多个MOSFET
公开(公告)号：US06707139B2
公开(公告)日：2004-03-16
申请号：US09928497
申请日：2001-08-14
申请人： Isamu Fujii , Kiyoshi Nakai , Yukihide Suzuki , Sadayuki Morita , Hidekazu Egawa , Katura Abe , Noriaki Sakamoto
发明人： Isamu Fujii , Kiyoshi Nakai , Yukihide Suzuki , Sadayuki Morita , Hidekazu Egawa , Katura Abe , Noriaki Sakamoto
IPC分类号： H01L2348
CPC分类号： H01L27/10897 , G11C5/025 , G11C11/4097 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection, via the second interconnection, according to combinations with the wiring dedicated areas adjacent thereto, as needed.
摘要翻译：具有用于实现特定逻辑电路的一个至多个MOSFET的多个单位区域被放置在第一方向上。在每个单位区域上形成沿第一方向延伸的第一互连。沿着第一方向延伸的第二互连沿着多个单元区域和单元区域外部形成。在相邻的单元区域之间分别设置具有沿与第一方向相交的第二方向延伸的第三互连的配线专用区域。根据需要，在每个单位区域中形成的逻辑电路具有连接到第一互连的第一连接形式和经由第二互连连接到第三互连的第二连接形式。

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