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1. 发明申请

US20070176580A1 Semiconductor integrated circuit device 有权
公开(公告)号：US20070176580A1
公开(公告)日：2007-08-02
申请号：US11730733
申请日：2007-04-03
申请人： Hiroshi Toyoshima , Masahiko Nishiyama
发明人： Hiroshi Toyoshima , Masahiko Nishiyama
IPC分类号： G05F1/00
CPC分类号： G05F1/56
摘要： The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin. And, since the phase compensating resistor can take a considerably high resistance, the same characteristic can be achieved with a low capacitance of the phase compensating capacitor; thereby, the phase compensation becomes possible with a resistor and a capacitor having a smaller size than the pole/zero compensation with the internal supply voltage.

2. 发明申请

US20070120245A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070120245A1
公开(公告)日：2007-05-31
申请号：US11563312
申请日：2006-11-27
申请人： Yasuhiro YOSHIKAWA , Motoo Suwa , Hiroshi Toyoshima
发明人： Yasuhiro YOSHIKAWA , Motoo Suwa , Hiroshi Toyoshima
IPC分类号： H01L23/52
CPC分类号： H01L23/528 , H01L23/49838 , H01L23/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01079 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2224/05599
摘要： Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other. A major signal wiring of an external output system connected to the external output terminal, which may be a noise source, is made to be in a wiring layer distant from the semiconductor integrated circuit.
摘要翻译：从外部输出信号系统到能够并联输入/输出操作的外部输入信号系统的互感减小。半导体集成电路具有面向封装基板的多个外部连接端子，具有能够并行输入/输出操作的外部输入端子和外部输出端子作为外部连接端子的一部分。封装基板具有用于将外部连接端子和彼此对应的模块端子之间电连接的多个布线层。面向半导体集成电路的第一布线层具有用于连接外部输入端子和彼此对应的模块端子之间的主要布线，并且其中形成模块端子的第二布线层具有用于连接外部输出端子和对应的模块端子。连接到可能是噪声源的外部输出端子的外部输出系统的主要信号布线被制成在远离半导体集成电路的布线层中。

3. 发明授权

US07208924B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07208924B2
公开(公告)日：2007-04-24
申请号：US10452045
申请日：2003-06-03
申请人： Hiroshi Toyoshima , Masahiko Nishiyama
发明人： Hiroshi Toyoshima , Masahiko Nishiyama
IPC分类号： G05F1/40 , G05F1/44 , H02H7/00
CPC分类号： G05F1/56
摘要： The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin. And, since the phase compensating resistor can take a considerably high resistance, the same characteristic can be achieved with a low capacitance of the phase compensating capacitor; thereby, the phase compensation becomes possible with a resistor and a capacitor having a smaller size than the pole/zero compensation with the internal supply voltage.
摘要翻译：本发明旨在提供一种容易实现足够的相位裕度的技术。电路包括在差分放大器的第二输入端子与低电源电压之间形成有相位补偿电阻器和相位补偿电容器的电源电路。因此，总增益中的第一极点频率由偏移到较低频率的极点/零点补偿的波德图中的分压电阻级中的第一极点频率决定。此外，零点消除差分放大器级中的第一极点频率，这降低了相位延迟以确保相位裕度。并且，由于相位补偿电阻器可以具有相当高的电阻，所以可以通过相位补偿电容器的低电容实现相同的特性; 由此，电阻和电容器的尺寸比内部电源电压的极/零补偿小的相位补偿成为可能。

4. 发明申请

US20060279340A1 Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件
公开(公告)号：US20060279340A1
公开(公告)日：2006-12-14
申请号：US11450424
申请日：2006-06-12
申请人： Hiroshi Toyoshima
发明人： Hiroshi Toyoshima
IPC分类号： H03B1/00
CPC分类号： H03K19/00323
摘要： A dummy MOSFET is provided which is connected in common with the gate of an N channel output MOSFET that constitutes a CMOS output circuit and which is set so as to have a gate capacitance corresponding to a difference between a gate capacitance of a P channel output MOSFET that constitutes the CMOS output circuit and a gate capacitance of the N channel output MOSFET. An input capacitance of the N channel output MOSFET and an input capacitance of the P channel output MOSFET are set equal to each other.
摘要翻译：提供了一个虚拟MOSFET，其与构成CMOS输出电路的N沟道输出MOSFET的栅极共同连接，并被设置为具有对应于P沟道输出MOSFET的栅极电容之间的差的栅极电容构成CMOS输出电路和N沟道输出MOSFET的栅极电容。 N沟道输出MOSFET的输入电容和P沟道输出MOSFET的输入电容彼此相等。

5. 发明授权

US5740115A Semiconductor memory device 失效
公开(公告)号：US5740115A
公开(公告)日：1998-04-14
申请号：US498969
申请日：1995-07-06
申请人： Koichiro Ishibashi , Kunihiro Komiyaji , Kiyotsugu Ueda , Hiroshi Toyoshima
发明人： Koichiro Ishibashi , Kunihiro Komiyaji , Kiyotsugu Ueda , Hiroshi Toyoshima
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22
摘要： A semiconductor memory device is provided which is able to supply data at high speed to a microprocessor (MPU) without being affected by the dispersion of power supply voltage, temperature and production process conditions. A semiconductor chip includes an address buffer, a decoder, a word driver, data lines, a sense amplifier, a main amplifier, an output buffer, and a PLL to which an external clock is applied. The PLL generates controls signals .PHI..sub.1 through .PHI..sub.7 with their phases shifted in turn, and supplies them to those internal circuits ranging from the address buffer to the output buffer. The PLL can control the phases of these control signals to be constant without being affected by the variations of temperature and power supply voltage. Thus, the internal circuits are precharged or equalized by the control signals, and then operated by the control signals to amplify data signal in turn. Therefore, the operating cycle time can be shortened as compared with the access time, and the access time can be kept constant.

6. 发明授权

US07800214B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07800214B2
公开(公告)日：2010-09-21
申请号：US11563312
申请日：2006-11-27
申请人： Yasuhiro Yoshikawa , Motoo Suwa , Hiroshi Toyoshima
发明人： Yasuhiro Yoshikawa , Motoo Suwa , Hiroshi Toyoshima
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/528 , H01L23/49838 , H01L23/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01079 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2224/05599
摘要： Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other. A major signal wiring of an external output system connected to the external output terminal, which may be a noise source, is made to be in a wiring layer distant from the semiconductor integrated circuit.
摘要翻译：从外部输出信号系统到能够并联输入/输出操作的外部输入信号系统的互感减小。半导体集成电路具有面向封装基板的多个外部连接端子，具有能够并行输入/输出操作的外部输入端子和外部输出端子作为外部连接端子的一部分。封装基板具有用于将外部连接端子和彼此对应的模块端子之间电连接的多个布线层。面向半导体集成电路的第一布线层具有用于连接外部输入端子和彼此对应的模块端子之间的主要布线，并且其中形成模块端子的第二布线层具有用于连接外部输出端子和对应的模块端子。连接到可能是噪声源的外部输出端子的外部输出系统的主要信号布线被制成在远离半导体集成电路的布线层中。

7. 发明授权

US07320482B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07320482B2
公开(公告)日：2008-01-22
申请号：US11730733
申请日：2007-04-03
申请人： Hiroshi Toyoshima , Masahiko Nishiyama
发明人： Hiroshi Toyoshima , Masahiko Nishiyama
IPC分类号： G05F1/40 , G05F1/44 , H02H7/00
CPC分类号： G05F1/56
摘要： The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin. And, since the phase compensating resistor can take a considerably high resistance, the same characteristic can be achieved with a low capacitance of the phase compensating capacitor; thereby, the phase compensation becomes possible with a resistor and a capacitor having a smaller size than the pole/zero compensation with the internal supply voltage.
摘要翻译：本发明旨在提供一种容易实现足够的相位裕度的技术。电路包括在差分放大器的第二输入端子与低电源电压之间形成有相位补偿电阻器和相位补偿电容器的电源电路。因此，总增益中的第一极点频率由偏移到较低频率的极点/零点补偿的波德图中的分压电阻级中的第一极点频率决定。此外，零点消除差分放大器级中的第一极点频率，这降低了相位延迟以确保相位裕度。并且，由于相位补偿电阻器可以具有相当高的电阻，所以可以通过相位补偿电容器的低电容实现相同的特性; 由此，电阻和电容器的尺寸比内部电源电压的极/零补偿小的相位补偿成为可能。

8. 发明授权

US06046609A Sense amplifier circuit 有权
标题翻译：感应放大电路
公开(公告)号：US06046609A
公开(公告)日：2000-04-04
申请号：US188369
申请日：1998-11-10
申请人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
发明人： Hiroshi Toyoshima , Masashige Harada , Tomohiro Nagano , Yoji Nishio , Atsushi Hiraishi , Kunihiro Komiyaji , Hideharu Yahata , Kenichi Fukui , Hirofumi Zushi , Takahiro Sonoda , Haruko Kawachino , Sadayuki Morita
IPC分类号： G11C11/419 , G11C7/06 , G11C11/409
CPC分类号： G11C7/065
摘要： A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
摘要翻译：一种读出放大器，其目的是在输出放大的输出信号之后，在接收到小的电压差之后，减小输出响应时间，由一对CMOS反相器构成的锁存电路，并联的一对NMOS晶体管到锁存电路，以及与锁存电路和NMOS晶体管对串联的电流源。 NMOS晶体管放大输入信号的小电压差，并且锁存电路的反相器进一步放大所产生的电压差以产生输出信号。基于两级放大的输入信号的小电压差，并且放大电路是电流源和NMOS晶体管或CMOS反相器的2级串联，可以降低输出响应的延迟时间。

9. 发明授权

US5930197A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5930197A
公开(公告)日：1999-07-27
申请号：US901771
申请日：1997-07-28
申请人： Koichiro Ishibashi , Kunihiro Komiyaji , Kiyotsugu Ueda , Hiroshi Toyoshima
发明人： Koichiro Ishibashi , Kunihiro Komiyaji , Kiyotsugu Ueda , Hiroshi Toyoshima
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22
摘要： A semiconductor memory device is provided which is able to supply data at high speed to a microprocessor (MPU) without being affected by the dispersion of power supply voltage, temperature and production process conditions. A semiconductor chip includes an address buffer, a decoder, a word driver, data lines, a sense amplifier, a main amplifier, an output buffer, and a PLL to which an external clock is applied. The PLL generates controls signals .PHI..sub.1 through .PHI..sub.7 with their phases shifted in turn, and supplies them to those internal circuits ranging from the address buffer to the output buffer. The PLL can control the phases of these control signals to be constant without being affected by the variations of temperature and power supply voltage. Thus, the internal circuits are precharged or equalized by the control signals, and then operated by the control signals to amplify data signal in turn. Therefore, the operating cycle time can be shortened as compared with the access time, and the access time can be kept constant.
摘要翻译：提供一种半导体存储器件，其能够高速地向微处理器（MPU）提供数据，而不受电源电压，温度和生产工艺条件的分散的影响。半导体芯片包括地址缓冲器，解码器，字驱动器，数据线，读出放大器，主放大器，输出缓冲器和施加了外部时钟的PLL。 PLL产生控制信号PHI 1至PHI 7，其相位依次移位，并将它们提供给从地址缓冲器到输出缓冲器的那些内部电路。 PLL可以将这些控制信号的相位控制为恒定，而不受温度和电源电压的变化的影响。因此，内部电路被控制信号预充电或均衡，然后由控制信号进行操作以依次放大数据信号。因此，与访问时间相比，可以缩短操作周期时间，并且可以保持访问时间不变。

10. 发明申请

US20080211548A1 Semiconductor integrated circuit controlling output impedance and slew rate 审中-公开
公开(公告)号：US20080211548A1
公开(公告)日：2008-09-04
申请号：US12149182
申请日：2008-04-29
申请人： Atsuhiro Hayashi , Takemi Negishi , Hiroshi Toyoshima
发明人： Atsuhiro Hayashi , Takemi Negishi , Hiroshi Toyoshima
IPC分类号： H03B1/00
CPC分类号： H03K19/018557 , H03K17/163 , H03K17/164 , H03K19/0005 , H03K19/00384 , H03K19/018585
摘要： The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.

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