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1. 发明申请

US20060237786A1 Power semiconductor device 审中-公开
标题翻译：功率半导体器件
公开(公告)号：US20060237786A1
公开(公告)日：2006-10-26
申请号：US11384260
申请日：2006-03-21
申请人： Hideaki Ninomiya , Masanobu Tsuchitani , Satoshi Teramae , Masakazu Yamaguchi , Koichi Sugiyama , Satoshi Urano , Keiko Kawamura
发明人： Hideaki Ninomiya , Masanobu Tsuchitani , Satoshi Teramae , Masakazu Yamaguchi , Koichi Sugiyama , Satoshi Urano , Keiko Kawamura
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/0623 , H01L29/0653 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/7393
摘要： A power semiconductor device according to the present invention comprises: a first conductive type base layer; a second conductive type base layer selectively formed on the first conductive type base layer; an insulation layer formed in the region on the first conductive type base layer on which the second conductive type base layer is not formed; a gate insulation film formed on the inner surface of a trench formed between the second conductive type base layer and the insulation layer so as to separate them from each other and to reach the first conductive type base layer from the surface of the second conductive type base layer; a first conductive type source layer selectively formed on the surface of the second conductive type base layer in contact with the gate insulation film; a gate electrode formed in the trench and insulated from the first conductive type base layer, the second conductive type base layer, and the first conductive type source layer by the gate insulation film; a main electrode electrically connected to the first conductive type base layer and the second conductive type base layer; and a first conductive type or second conductive type floating layer formed on the bottom of the insulation layer.
摘要翻译：根据本发明的功率半导体器件包括：第一导电型基极层; 选择性地形成在所述第一导电型基底层上的第二导电型基底层; 形成在不形成第二导电型基底层的第一导电型基底层上的区域中的绝缘层; 形成在形成在第二导电型基极层和绝缘层之间的沟槽的内表面上以便将它们彼此分离并从第二导电类型基底的表面到达第一导电型基极的栅极绝缘膜层; 选择性地形成在与所述栅极绝缘膜接触的所述第二导电型基底层的表面上的第一导电型源极层; 形成在所述沟槽中的栅电极，通过所述栅极绝缘膜与所述第一导电型基极层，所述第二导电型基极层和所述第一导电型源极绝缘; 电连接到第一导电型基极层和第二导电型基极层的主电极; 以及形成在绝缘层的底部上的第一导电型或第二导电型浮动层。

2. 发明授权

US07772641B2 Power semiconductor device with a plurality of gate electrodes 有权
标题翻译：具有多个栅电极的功率半导体器件
公开(公告)号：US07772641B2
公开(公告)日：2010-08-10
申请号：US11682670
申请日：2007-03-06
申请人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
发明人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
IPC分类号： H01L29/80
CPC分类号： H01L29/7397 , H01L23/4824 , H01L29/0619 , H01L29/0696 , H01L29/41775 , H01L29/4236 , H01L29/66348 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.
摘要翻译：功率半导体器件包括：半导体层，具有沿条形配置沿着第一方向延伸的沟槽; 掩埋在所述沟槽中的用于控制在所述半导体层中流动的电流的栅电极; 以及由具有比栅极电极更高的导电性的材料制成的栅极插塞，栅极插塞具有带状结构，并沿第一方向连接到栅电极。半导体层包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层，部分地设置在第一半导体层的上表面上; 第一导电类型的第三半导体层部分地设置在第二半导体层上; 以及设置在第一半导体层的下表面上的第二导电类型的第四半导体层。

3. 发明申请

US20070210350A1 POWER SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND METHOD FOR DRIVING SAME 有权
标题翻译：功率半导体器件，其制造方法及其驱动方法
公开(公告)号：US20070210350A1
公开(公告)日：2007-09-13
申请号：US11682670
申请日：2007-03-06
申请人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
发明人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
IPC分类号： H01L29/80
CPC分类号： H01L29/7397 , H01L23/4824 , H01L29/0619 , H01L29/0696 , H01L29/41775 , H01L29/4236 , H01L29/66348 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.
摘要翻译：功率半导体器件包括：半导体层，具有沿条形配置沿着第一方向延伸的沟槽; 掩埋在所述沟槽中的用于控制在所述半导体层中流动的电流的栅电极; 以及由具有比栅极电极更高的导电性的材料制成的栅极插塞，栅极插塞具有带状结构，并沿第一方向连接到栅电极。半导体层包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层，部分地设置在第一半导体层的上表面上; 第一导电类型的第三半导体层部分地设置在第二半导体层上; 以及设置在第一半导体层的下表面上的第二导电类型的第四半导体层。

4. 发明授权

US07507630B2 Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07507630B2
公开(公告)日：2009-03-24
申请号：US11299907
申请日：2005-12-13
申请人： Masanobu Tsuchitani , Hitoshi Shinohara , Keiko Kawamura
发明人： Masanobu Tsuchitani , Hitoshi Shinohara , Keiko Kawamura
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L29/7811
摘要： A method of fabricating a semiconductor device includes: forming an insulating film on a semiconductor body to cover a termination area surrounding a cell area; forming a mask material film to cover the cell area and the insulating film; forming a resist film to cover the mask material film; patterning the resist film to have an opening serving as a gate-use resist pattern above the cell area and another opening serving as a dummy resist pattern above the insulating film; selectively etching the mask material film by use of the patterned resist film as a mask so that the insulating film is remained under the dummy resist pattern; selectively etching the semiconductor body by use of the patterned mask material film as another mask to form a trench in the cell area as corresponding to the gate-use resist pattern; and burying gate material in the trench to form the trench gate.
摘要翻译：制造半导体器件的方法包括：在半导体本体上形成绝缘膜以覆盖围绕单元区域的端接区域; 形成掩模材料膜以覆盖单元区域和绝缘膜; 形成抗蚀剂膜以覆盖掩模材料膜; 将抗蚀剂膜图案化成在单元区域之上具有用作栅极用途抗蚀剂图案的开口，并且在绝缘膜上方具有用作模拟抗蚀剂图案的另一开口; 通过使用图案化的抗蚀剂膜作为掩模来选择性地蚀刻掩模材料膜，使得绝缘膜保持在假抗蚀剂图案下方; 通过使用图案化掩模材料膜作为另一掩模来选择性地蚀刻半导体本体，以在对应于栅极使用抗蚀剂图案的单元区域中形成沟槽; 并将栅极材料埋入沟槽中以形成沟槽栅极。

5. 发明申请

US20060091453A1 Trench MIS device and method for manufacturing trench MIS device 审中-公开
标题翻译：沟槽MIS器件及其制造沟槽MIS器件的方法
公开(公告)号：US20060091453A1
公开(公告)日：2006-05-04
申请号：US11208619
申请日：2005-08-23
申请人： Noboru Matsuda , Koichi Takahashi , Keiko Kawamura , Masanobu Tsuchitani
发明人： Noboru Matsuda , Koichi Takahashi , Keiko Kawamura , Masanobu Tsuchitani
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/42368 , H01L29/515 , H01L29/66734
摘要： A trench MIS device includes a drain region, a base region disposed on the drain region, the base region having a channel face, a source region disposed on the base region, the source region having a source end face, the source end face being continuous with the channel face, a gate insulator disposed along the channel face and the source end face, a gate electrode disposed opposite to the channel face through the gate insulator, and a cavity portion provided in the drain region, the cavity portion being opposite to the gate electrode.
摘要翻译：沟槽MIS器件包括漏极区域，设置在漏极区域上的基极区域，具有沟道面的基极区域，设置在基极区域上的源极区域，源极区域具有源极端面，源极端面连续所述沟道面具有沿沟道面和源极端面配置的栅极绝缘体，通过栅极绝缘体与沟道面相对设置的栅极电极和设置在漏极区域中的空腔部分，空腔部分与漏极区域相对栅电极。

6. 发明授权

US07541642B2 Semiconductor device with a gate electrode including a pair of polysilicon layers 失效
标题翻译：具有包括一对多晶硅层的栅电极的半导体器件
公开(公告)号：US07541642B2
公开(公告)日：2009-06-02
申请号：US11245042
申请日：2005-10-07
申请人： Keiko Kawamura , Masanobu Tsuchitani
发明人： Keiko Kawamura , Masanobu Tsuchitani
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/66727 , H01L29/66734 , H01L29/7397
摘要： A semiconductor device comprises a semiconductor substrate having a gate trench formed therein. A gate electrode is formed on a gate insulator in the gate trench. The gate electrode has ends close to the bottom of the gate trench, which are separated in a direction perpendicular to both sides of the gate trench, and portions except the separated ends, at least part of which is made higher in conductivity than other parts.
摘要翻译：半导体器件包括其中形成有栅极沟槽的半导体衬底。栅极电极形成在栅极沟槽中的栅极绝缘体上。栅电极具有靠近栅极沟槽的底部的端部，栅极沟槽的底部沿垂直于栅极沟槽两侧的方向分开，以及除了分离端部以外的部分，其至少一部分的导电率比其它部分高。

7. 发明申请

US20070023828A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070023828A1
公开(公告)日：2007-02-01
申请号：US11245042
申请日：2005-10-07
申请人： Keiko Kawamura , Masanobu Tsuchitani
发明人： Keiko Kawamura , Masanobu Tsuchitani
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/41766 , H01L29/4236 , H01L29/4238 , H01L29/456 , H01L29/4925 , H01L29/66727 , H01L29/66734 , H01L29/7397
摘要： A semiconductor device comprises a semiconductor substrate having a gate trench formed therein. A gate electrode is formed on a gate insulator in the gate trench. The gate electrode has ends close to the bottom of the gate trench, which are separated in a direction perpendicular to both sides of the gate trench, and portions except the separated ends, at least part of which is made higher in conductivity than other parts.
摘要翻译：半导体器件包括其中形成有栅极沟槽的半导体衬底。栅极电极形成在栅极沟槽中的栅极绝缘体上。栅电极具有靠近栅极沟槽的底部的端部，栅极沟槽的底部沿垂直于栅极沟槽两侧的方向分开，以及除了分离端部以外的部分，其至少一部分的导电率比其它部分高。

8. 发明申请

US20060160320A1 Method of fabricating a semiconductor device 失效
公开(公告)号：US20060160320A1
公开(公告)日：2006-07-20
申请号：US11299907
申请日：2005-12-13
申请人： Masanobu Tsuchitani , Hitoshi Shinohara , Keiko Kawamura
发明人： Masanobu Tsuchitani , Hitoshi Shinohara , Keiko Kawamura
IPC分类号： H01L21/76
CPC分类号： H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L29/7811
摘要： A method of fabricating a semiconductor device includes: forming an insulating film on a semiconductor body to cover a termination area surrounding a cell area; forming a mask material film to cover the cell area and the insulating film; forming a resist film to cover the mask material film; patterning the resist film to have an opening serving as a gate-use resist pattern above the cell area and another opening serving as a dummy resist pattern above the insulating film; selectively etching the mask material film by use of the patterned resist film as a mask so that the insulating film is remained under the dummy resist pattern; selectively etching the semiconductor body by use of the patterned mask material film as another mask to form a trench in the cell area as corresponding to the gate-use resist pattern; and burying gate material in the trench to form the trench gate.

9. 发明申请

US20060145290A1 Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type 审中-公开
公开(公告)号：US20060145290A1
公开(公告)日：2006-07-06
申请号：US11294411
申请日：2005-12-06
申请人： Hideki Okumura , Hitoshi Kobayashi , Masanobu Tsuchitani , Akihiko Osawa , Wataru Saito , Masakazu Yamaguchi , Ichiro Omura
发明人： Hideki Okumura , Hitoshi Kobayashi , Masanobu Tsuchitani , Akihiko Osawa , Wataru Saito , Masakazu Yamaguchi , Ichiro Omura
IPC分类号： H01L29/00 , H01L21/425 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/7802
摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

10. 发明授权

US06995426B2 Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type 有权
标题翻译：具有垂直金属绝缘体半导体晶体管的半导体器件具有不同导电类型的多个空间重叠区域
公开(公告)号：US06995426B2
公开(公告)日：2006-02-07
申请号：US10327937
申请日：2002-12-26
申请人： Hideki Okumura , Hitoshi Kobayashi , Masanobu Tsuchitani , Akihiko Osawa , Wataru Saito , Masakazu Yamaguchi , Ichiro Omura
发明人： Hideki Okumura , Hitoshi Kobayashi , Masanobu Tsuchitani , Akihiko Osawa , Wataru Saito , Masakazu Yamaguchi , Ichiro Omura
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/7802
摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.
摘要翻译：半导体器件包括形成在第一导电类型的半导体层中的扩散区域。扩散区域分别包括第一和第二导电类型的第一和第二杂质扩散区域。扩散区域具有由第一和第二杂质扩散区域的杂质浓度限定的第一和第二区域。第一和第二区域之间的结点形成在第一和第二杂质扩散区域彼此重叠的部分中。在第一或第二区域的半导体层的平面方向上的杂质浓度的周期小于半导体层的平面方向上的构成第一或第二区域的第一和第二杂质扩散区域的最大宽度第二区。

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