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1. 发明申请

US20110012251A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110012251A1
公开(公告)日：2011-01-20
申请号：US12833728
申请日：2010-07-09
申请人： Satoshi TERAMAE
发明人： Satoshi TERAMAE
IPC分类号： H01L23/04 , H01L21/56
CPC分类号： H01L23/24 , H01L23/562 , H01L24/48 , H01L25/072 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01079 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： According to one embodiment, a semiconductor device includes a base substrate, at least one semiconductor chip provided above the base substrate, and a resin case covering the semiconductor chip and supported by the base substrate. A partition plate holds back extension of a crack occurring in the resin case being provided in the resin case.
摘要翻译：根据一个实施例，半导体器件包括基底基板，设置在基底基板上方的至少一个半导体芯片以及覆盖半导体芯片并被基底基板支撑的树脂壳体。分隔板阻止在设置在树脂壳体中的树脂壳体中发生的裂缝的延伸。

2. 发明申请

US20060237786A1 Power semiconductor device 审中-公开
标题翻译：功率半导体器件
公开(公告)号：US20060237786A1
公开(公告)日：2006-10-26
申请号：US11384260
申请日：2006-03-21
申请人： Hideaki Ninomiya , Masanobu Tsuchitani , Satoshi Teramae , Masakazu Yamaguchi , Koichi Sugiyama , Satoshi Urano , Keiko Kawamura
发明人： Hideaki Ninomiya , Masanobu Tsuchitani , Satoshi Teramae , Masakazu Yamaguchi , Koichi Sugiyama , Satoshi Urano , Keiko Kawamura
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/0623 , H01L29/0653 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/7393
摘要： A power semiconductor device according to the present invention comprises: a first conductive type base layer; a second conductive type base layer selectively formed on the first conductive type base layer; an insulation layer formed in the region on the first conductive type base layer on which the second conductive type base layer is not formed; a gate insulation film formed on the inner surface of a trench formed between the second conductive type base layer and the insulation layer so as to separate them from each other and to reach the first conductive type base layer from the surface of the second conductive type base layer; a first conductive type source layer selectively formed on the surface of the second conductive type base layer in contact with the gate insulation film; a gate electrode formed in the trench and insulated from the first conductive type base layer, the second conductive type base layer, and the first conductive type source layer by the gate insulation film; a main electrode electrically connected to the first conductive type base layer and the second conductive type base layer; and a first conductive type or second conductive type floating layer formed on the bottom of the insulation layer.
摘要翻译：根据本发明的功率半导体器件包括：第一导电型基极层; 选择性地形成在所述第一导电型基底层上的第二导电型基底层; 形成在不形成第二导电型基底层的第一导电型基底层上的区域中的绝缘层; 形成在形成在第二导电型基极层和绝缘层之间的沟槽的内表面上以便将它们彼此分离并从第二导电类型基底的表面到达第一导电型基极的栅极绝缘膜层; 选择性地形成在与所述栅极绝缘膜接触的所述第二导电型基底层的表面上的第一导电型源极层; 形成在所述沟槽中的栅电极，通过所述栅极绝缘膜与所述第一导电型基极层，所述第二导电型基极层和所述第一导电型源极绝缘; 电连接到第一导电型基极层和第二导电型基极层的主电极; 以及形成在绝缘层的底部上的第一导电型或第二导电型浮动层。

3. 发明申请

US20050280078A1 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US20050280078A1
公开(公告)日：2005-12-22
申请号：US11154743
申请日：2005-06-17
申请人： Satoshi Teramae , Shigeru Hasegawa , Hideaki Ninomiya , Masahiro Tanaka
发明人： Satoshi Teramae , Shigeru Hasegawa , Hideaki Ninomiya , Masahiro Tanaka
IPC分类号： H01L21/336 , H01L29/06 , H01L29/10 , H01L29/417 , H01L29/739 , H01L29/76
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/41741
摘要： An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate so as to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the device region and divided in segments by insulated trench-shaped gates so as to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, and a connection part to electrically connect the peripheral diffusion region to the emitter electrode.
摘要翻译：一种绝缘栅半导体器件，包括沿着半导体衬底的周边形成在循环部分中的隔离结构，以将该部分与内部器件区域隔离，位于隔离结构外部的半导体衬底的外围扩散区域，多个在器件区域中定义并由绝缘的沟槽状栅极划分成段的单元结构，以便在其上表面上覆盖有发射极区域的基极区域，集电极区域和电连接到发射极区域的发射极电极，所述基极区域，与所述单元结构邻接的虚设基极区域，并且被配置为其上表面保持没有发射极区域连接到所述发射极的基极区域;以及连接部分，用于将所述外围扩散区域电连接到所述发射极电极。

4. 发明授权

US5708299A Multichip press-contact type semiconductor device 失效
标题翻译：多芯片压接式半导体器件
公开(公告)号：US5708299A
公开(公告)日：1998-01-13
申请号：US656868
申请日：1996-05-30
申请人： Satoshi Teramae , Michiaki Hiyoshi
发明人： Satoshi Teramae , Michiaki Hiyoshi
IPC分类号： H01L21/52 , H01L23/48 , H01L23/58 , H01L25/07 , H01L25/18 , H01L29/78 , H01L29/74 , H01L23/42
CPC分类号： H01L24/72 , H01L25/072 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/12035 , H01L2924/1305 , H01L2924/13055 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107
摘要： IGBT chips and FRD chips are arranged on the same plane so as to be press-contacted by an emitter press-contact electrode plate and a collector press-contact electrode plate at the same time. The FRD chips are arranged at a central portion, and the IGBT chips are arranged at the peripheral portion of the FRD chips. A resin substrate having an opening in its contact portion between a main surface of each of said chip and the emitter press-contact electrode plate is provided between both press-contact electrode plates. Gate press-contact electrodes are formed on the resin substrate to be electrically connected to a gate electrode of each of the IGBT chips. Also, gate wires are fixed to the resin substrate to supply a control signal for controlling the IGBT chips to the gate electrode of the IGBT chips from the gate wires through the gate press-contact electrode.
摘要翻译： IGBT芯片和FRD芯片布置在同一平面上，以便同时由发射体压接电极板和集电体压接电极板压接。 FRD芯片布置在中心部分，并且IGBT芯片布置在FRD芯片的周边部分。在两个压接电极板之间设置有在其每个所述芯片的主表面和发射极压接电极板之间的接触部分中具有开口的树脂基板。栅极压接电极形成在树脂基板上以与每个IGBT芯片的栅电极电连接。此外，栅极线固定到树脂基板，以通过栅极压接电极从栅极线提供用于控制IGBT芯片到IGBT芯片的栅电极的控制信号。

5. 发明授权

US09041052B2 Semiconductor device, semiconductor unit, and power semiconductor device 有权
标题翻译：半导体器件，半导体单元和功率半导体器件
公开(公告)号：US09041052B2
公开(公告)日：2015-05-26
申请号：US13052025
申请日：2011-03-18
申请人： Satoshi Teramae
发明人： Satoshi Teramae
IPC分类号： H01L27/12 , H01L25/07 , H01L23/373 , H01L23/498 , H01L23/00 , H05K1/02 , H01L23/04 , H01L23/049 , H01L23/24 , H05K3/00 , H05K3/22
CPC分类号： H01L25/072 , H01L23/04 , H01L23/049 , H01L23/24 , H01L23/3735 , H01L23/49838 , H01L24/29 , H01L24/32 , H01L24/45 , H01L2224/29101 , H01L2224/32013 , H01L2224/32238 , H01L2224/45124 , H01L2224/83447 , H01L2224/83801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01322 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/15787 , H01L2924/19107 , H01L2924/351 , H05K1/0209 , H05K3/0061 , H05K3/222 , H05K2201/09663 , H05K2201/0969 , H05K2201/1028 , H05K2201/10287 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device includes: an insulating substrate; a first electrode pattern and a second electrode pattern provided apart from each other on a major surface of the insulating substrate; a semiconductor element connected to the first electrode pattern; an electrode terminal connected to the second electrode pattern; and a connection wiring. The connection wiring electrically connects the first electrode pattern and the second electrode pattern with each other and has a thermal resistance larger than that of the first electrode pattern.
摘要翻译：半导体器件包括：绝缘基板; 在所述绝缘基板的主表面上彼此分开设置的第一电极图案和第二电极图案; 连接到第一电极图案的半导体元件; 连接到第二电极图案的电极端子; 和连接线。连接布线将第一电极图案和第二电极图案彼此电连接并且具有比第一电极图案的热阻大的热阻。

6. 发明授权

US07211861B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US07211861B2
公开(公告)日：2007-05-01
申请号：US11154743
申请日：2005-06-17
申请人： Satoshi Teramae , Shigeru Hasegawa , Hideaki Ninomiya , Masahiro Tanaka
发明人： Satoshi Teramae , Shigeru Hasegawa , Hideaki Ninomiya , Masahiro Tanaka
IPC分类号： H01L29/06
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/41741
摘要： An insulated gate semiconductor device, includes an isolating structure shaped in a circulating section along the periphery of a semiconductor substrate to isolate that part from an inside device region, a peripheral diffusion region of the semiconductor substrate located outside the isolating structure, a plurality of cell structures defined in the inside device region and divided in segments by insulated trench-shaped gates to have a base region covered with an emitter region in its upper surface, a collector region, and an emitter electrode electrically connected to the emitter region and the base region, a dummy base region contiguous to the cell structures and configured as a base region that has its upper surface left without the emitter region connected to the emitter electrode, an inner region defined in and insulated from the dummy base region, and a connection part to electrically connect the inner region to the emitter electrode.
摘要翻译：一种绝缘栅半导体器件，包括沿着半导体衬底的周边形成在循环部分中的隔离结构，以将该部分与内部器件区域隔离，位于隔离结构外部的半导体衬底的外围扩散区域，多个电池单元在内部器件区域中限定的结构，并由绝缘的沟槽形状的栅极分割成具有覆盖在其上表面的发射极区域的基极区域，集电极区域和与发射极区域和基极区域电连接的发射极电极，与单元结构邻接的虚拟基极区域，并且被配置为具有其上表面没有发射极区域连接到发射极电极的基极区域，限定在虚拟基极区域中并与虚拟基极区域绝缘的内部区域，以及连接部分将内部区域电连接到发射极。

7. 外观设计

USD503149S1 Power converter 失效
公开(公告)号：USD503149S1
公开(公告)日：2005-03-22
申请号：US29193447
申请日：2003-11-12
申请人： Satoshi Teramae , Yoko Sakiyama
设计人： Satoshi Teramae , Yoko Sakiyama

8. 发明申请

US20110284924A1 SEMICONDUCTOR DEVICE, SEMICONDUCTOR UNIT, AND POWER SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件，半导体器件和功率半导体器件
公开(公告)号：US20110284924A1
公开(公告)日：2011-11-24
申请号：US13052025
申请日：2011-03-18
申请人： Satoshi TERAMAE
发明人： Satoshi TERAMAE
IPC分类号： H01L29/739 , H01L27/12
CPC分类号： H01L25/072 , H01L23/04 , H01L23/049 , H01L23/24 , H01L23/3735 , H01L23/49838 , H01L24/29 , H01L24/32 , H01L24/45 , H01L2224/29101 , H01L2224/32013 , H01L2224/32238 , H01L2224/45124 , H01L2224/83447 , H01L2224/83801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01322 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/15787 , H01L2924/19107 , H01L2924/351 , H05K1/0209 , H05K3/0061 , H05K3/222 , H05K2201/09663 , H05K2201/0969 , H05K2201/1028 , H05K2201/10287 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device includes: an insulating substrate; a first electrode pattern and a second electrode pattern provided apart from each other on a major surface of the insulating substrate; a semiconductor element connected to the first electrode pattern; an electrode terminal connected to the second electrode pattern; and a connection wiring. The connection wiring electrically connects the first electrode pattern and the second electrode pattern with each other and has a thermal resistance larger than that of the first electrode pattern.
摘要翻译：半导体器件包括：绝缘基板; 在所述绝缘基板的主表面上彼此分开设置的第一电极图案和第二电极图案; 连接到第一电极图案的半导体元件; 连接到第二电极图案的电极端子; 和连接线。连接布线将第一电极图案和第二电极图案彼此电连接并且具有比第一电极图案的热阻大的热阻。

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