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1. 发明授权

US5231041A Manufacturing method of an electrically programmable non-volatile memory device having the floating gate extending over the control gate 失效
标题翻译：具有在控制栅极上延伸的浮动栅极的电可编程非易失性存储器件的制造方法
公开(公告)号：US5231041A
公开(公告)日：1993-07-27
申请号：US819206
申请日：1992-01-10
申请人： Hideaki Arima , Yoshinori Okumura , Hideki Genjo , Ikuo Ogoh , Kohjiroh Yuzuriha , Yuichi Nakashima
发明人： Hideaki Arima , Yoshinori Okumura , Hideki Genjo , Ikuo Ogoh , Kohjiroh Yuzuriha , Yuichi Nakashima
IPC分类号： H01L21/8247 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L29/42332 , H01L29/7886
摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layer disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.
摘要翻译：公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层设置在它们之间，并且浮置栅极形成为在控制电极的上表面和一个侧面之间设置绝缘层。在控制栅极的相对侧的硅衬底中产生漏极和源极区。在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极存储数据代表费用。闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

2. 发明授权

US5101250A Electrically programmable non-volatile memory device and manufacturing method thereof 失效
标题翻译：电可编程非易失性存储器件及其制造方法
公开(公告)号：US5101250A
公开(公告)日：1992-03-31
申请号：US630439
申请日：1990-12-20
申请人： Hideaki Arima , Yoshinori Okumura , Hideki Genjo , Ikuo Ogoh , Kohjiroh Yuzuriha , Yuichi Nakashima
发明人： Hideaki Arima , Yoshinori Okumura , Hideki Genjo , Ikuo Ogoh , Kohjiroh Yuzuriha , Yuichi Nakashima
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L29/42332 , H01L29/7886
摘要： A 1-transistor type flash EEPROM is disclosed. The memory cell in the EEPROM includes a control gate formed on a silicon substrate with an insulating layer disposed between them, and a floating gate formed to extend over the upper face and one side face of the control electrode with an insulating layers disposed between them. Drain and source regions are created in the silicon substrate on the opposite sides of the control gate. The area in the silicon substrate under the control gate between the drain and source regions defines a channel region. In the EEPROM, an application of high-level voltage to the control gate and the drain region produces hot electrons in the vicinity of the opposite ends of the drain region which are driven into the floating gate across the insulating layer, causing the floating gate to store data-representing charge. The flash EEPROM has uniform characteristics among memory cells and reduced cell area for improved miniaturization.
摘要翻译：公开了1晶体管型快闪EEPROM。 EEPROM中的存储单元包括形成在硅衬底上的控制栅极，绝缘层位于它们之间，浮栅形成为在控制电极的上表面和一个侧面之间设置绝缘层。在控制栅极的相对侧的硅衬底中产生漏极和源极区。在漏极和源极区域之间的控制栅极下方的硅衬底中的区域限定沟道区域。在EEPROM中，向控制栅极和漏极区域施加高电平电压在漏极区域的相对端附近产生热电子，这些电极驱动跨越绝缘层的浮动栅极，从而使浮动栅极存储数据代表费用。闪存EEPROM在存储单元之间具有均匀的特性，并且减小了单元面积以改善小型化。

3. 发明授权

US5051948A Content addressable memory device 失效
标题翻译：内容可寻址存储设备
公开(公告)号：US5051948A
公开(公告)日：1991-09-24
申请号：US434692
申请日：1989-10-20
申请人： Kiyoto Watabe , Hirofumi Shinohara , Takahisa Eimori , Hideaki Arima , Natsuo Ajika , Yuichi Nakashima , Shinichi Satoh
发明人： Kiyoto Watabe , Hirofumi Shinohara , Takahisa Eimori , Hideaki Arima , Natsuo Ajika , Yuichi Nakashima , Shinichi Satoh
IPC分类号： G11C15/04
CPC分类号： G11C15/046
摘要： In a content addressable memory (CAM) cell according to the present invention, a pair of non-volatile memory transistors hold data, whereby stored data will not disappear even if power is cut. Conducting terminals of these non-volatile transistors are connected to a bit line pair, so that the stored data can be directly read out from the bit line pair. Further, the invention CAM system converts the value of a current flowing in a match line into a voltage value to perform content reference, and hence the same can be employed as an associative memory system.
摘要翻译： PCT No.PCT / JP89 / 00179 Sec。 371日期1989年10月20日第 102（e）日期1989年10月20日PCT提交1989年2月22日PCT公布。出版物WO89 / 08314 日本1989年9月8日。在根据本发明的内容可寻址存储器（CAM）单元中，一对非易失性存储晶体管保持数据，由此即使切断功率，存储的数据也不会消失。这些非易失性晶体管的导通端子连接到位线对，从而可以从位线对直接读出所存储的数据。此外，本发明CAM系统将在匹配线中流动的电流的值转换为电压值以执行内容参考，因此可以将其用作关联存储器系统。

4. 发明授权

US06617666B2 Semiconductor device with capacitor and process for manufacturing the device 失效
公开(公告)号：US06617666B2
公开(公告)日：2003-09-09
申请号：US10093114
申请日：2002-03-07
申请人： Takashi Yoshitomi , Yuichi Nakashima
发明人： Takashi Yoshitomi , Yuichi Nakashima
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L21/31116 , H01L21/31604 , H01L21/32136 , H01L21/76801 , H01L21/76834 , Y10S438/957
摘要： A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.

5. 发明授权

US5204540A Resin sealed semiconductor device for use in testing and evaluation method of stress due to resin seal 失效
标题翻译：树脂密封半导体器件用于由于树脂密封引起的应力测试和评估方法
公开(公告)号：US5204540A
公开(公告)日：1993-04-20
申请号：US673655
申请日：1991-03-21
申请人： Yuichi Nakashima , Shintaro Matsuda
发明人： Yuichi Nakashima , Shintaro Matsuda
IPC分类号： H01L21/56 , H01L21/66 , H01L23/28 , H01L23/544
CPC分类号： H01L22/34 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/49175 , H01L2924/1305 , H01L2924/13091 , H01L2924/181
摘要： A resin sealed semiconductor device for use in testing is disclosed, in which a first MOS field effect transistor is formed in a region within 100 .mu.m from an outer perimeter of a main surface of a silicon substrate, and a second MOS field effect transistor is formed in a region 100 .mu.m or more distant from an outer perimeter of the main surface, and the first and second MOS field effect transistors are encapsulated with resin. Dimensions and materials of the first MOS field effect transistor and the second MOS field effect transistor are identical. By comparing the electric characteristics of the first MOS field effect transistor and the electric characteristics of the second MOS field effect transistor, the effect produced on the MOS field effect transistors by the mechanical stresses due to the resin seal applied from a side direction of silicon substrate can be evaluated.
摘要翻译：公开了一种用于测试的树脂密封半导体器件，其中第一MOS场效应晶体管形成在距离硅衬底的主表面的外周边100μm以内的区域中，第二MOS场效应晶体管是形成在远离主表面的外周边100μm或更远的区域中，第一和第二MOS场效应晶体管被树脂封装。第一MOS场效应晶体管和第二MOS场效应晶体管的尺寸和材料相同。通过比较第一MOS场效应晶体管的电特性和第二MOS场效应晶体管的电特性，通过由硅衬底的侧面方向施加的树脂密封的机械应力对MOS场效应晶体管产生的影响可以评估。

6. 发明申请

US20070228573A1 SEMICONDUCTOR DEVICE HAVING CAPACITOR FORMED IN MULTILAYER WIRING STRUCTURE 审中-公开
标题翻译：具有多层布线结构的电容器的半导体器件
公开(公告)号：US20070228573A1
公开(公告)日：2007-10-04
申请号：US11762432
申请日：2007-06-13
申请人： Takeshi MATSUNAGA , Yuichi Nakashima , Koji Miyamoto
发明人： Takeshi MATSUNAGA , Yuichi Nakashima , Koji Miyamoto
IPC分类号： H01L23/52
CPC分类号： H01L28/40 , H01L21/76838 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a capacitor formed in a multilayer wiring structure, the semiconductor device comprising a multilayer wiring structure including a plurality of wiring layers formed on a substrate, a capacitor arranged in a predetermined wiring layer in the multilayer wiring structure and having a lower electrode, a dielectric film, and an upper electrode, a first via formed in the predetermined wiring layer and connected to a top surface of the upper electrode of the capacitor, and a second via formed in an overlying wiring layer stacked on the predetermined wiring layer, the second via being formed on the first via.
摘要翻译：一种具有形成在多层布线结构中的电容器的半导体器件，所述半导体器件包括多层布线结构，所述多层布线结构包括形成在基板上的多个布线层，布置在所述多层布线结构中的预定布线层中并具有下电极介电膜和上电极，形成在预定布线层中并连接到电容器的上电极的顶表面的第一通孔，以及形成在叠置在预定布线层上的上覆布线层中的第二通孔，第二通孔形成在第一通孔上。

7. 发明授权

US5187558A Stress reduction structure for a resin sealed semiconductor device 失效
标题翻译：树脂密封半导体器件的应力减小结构
公开(公告)号：US5187558A
公开(公告)日：1993-02-16
申请号：US517628
申请日：1990-05-01
申请人： Yuichi Nakashima , Mitsuhiro Tomikawa , Hirohisa Yamamoto
发明人： Yuichi Nakashima , Mitsuhiro Tomikawa , Hirohisa Yamamoto
IPC分类号： H01L23/29 , H01L23/31 , H01L29/06
CPC分类号： H01L29/0657 , H01L23/298 , H01L23/3135 , H01L23/3178 , H01L24/05 , H01L2224/04042 , H01L2224/05 , H01L2224/05554 , H01L2224/05624 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/49175 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12036 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041
摘要： A resin sealed semiconductor device includes a semiconductor chip formed on a substrate and sealed with resin. A concave portion is formed on a major surface of a semiconductor substrate between an insulating film for isolation and an edge of the major surface of the semiconductor substrate. This concave portion is filled with a buffer member having an elastic modulus smaller than that of the material of the semiconductor substrate. Mechanical stress applied to an edge of the semiconductor substrate, caused by the callosity of resin, is absorbed and reduced by the buffer member. A portion of the semiconductor substrate between the concave portion and the insulating film for isolation prevents the remainder of the mechanical stress from being transmitted from the buffer member to the insulating film and circuit elements.
摘要翻译：树脂密封半导体器件包括形成在基板上并用树脂密封的半导体芯片。在绝缘绝缘膜和半导体衬底的主表面的边缘之间的半导体衬底的主表面上形成凹部。该凹部填充有弹性模量小于半导体衬底的材料的缓冲构件。施加到由树脂的胼los质引起的半导体衬底边缘的机械应力被缓冲构件吸收和减少。用于隔离的凹部和绝缘膜之间的半导体衬底的一部分防止其余的机械应力从缓冲构件传递到绝缘膜和电路元件。

8. 发明授权

US06864137B2 MIM capacitor with diffusion barrier 失效
标题翻译：具有扩散阻挡层的MIM电容器
公开(公告)号：US06864137B2
公开(公告)日：2005-03-08
申请号：US10619394
申请日：2003-07-15
申请人： Takashi Yoshitomi , Yuichi Nakashima
发明人： Takashi Yoshitomi , Yuichi Nakashima
IPC分类号： H01L23/52 , H01L21/02 , H01L21/304 , H01L21/311 , H01L21/316 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L21/822 , H01L27/04 , H01L21/8242
CPC分类号： H01L28/40 , H01L21/31116 , H01L21/31604 , H01L21/32136 , H01L21/76801 , H01L21/76834 , Y10S438/957
摘要： A process of manufacturing a semiconductor device. The initial process steps are forming a first insulating film above a semiconductor substrate and removing a selected portion of the first insulating film to form an opening. The next step is depositing a first electrode, a dielectric film and a second electrode successively on a bottom portion of the opening, The deposits being oriented such that they are in substantially parallel relationship with a surface of the semiconductor substrate. The final steps are removing selected portions of the first electrode, the dielectric film and the second electrode, forming a capacitor at a selected position in the opening, forming a second insulating film at least in the opening, and forming a third insulating film on the second insulating film.
摘要翻译：一种制造半导体器件的工艺。初始工艺步骤是在半导体衬底上形成第一绝缘膜，并去除第一绝缘膜的选定部分以形成开口。下一步是在开口的底部依次沉积第一电极，电介质膜和第二电极。沉积物取向为使得它们与半导体衬底的表面基本平行。最后的步骤是去除第一电极，电介质膜和第二电极的选定部分，在开口中的选定位置形成电容器，至少在开口中形成第二绝缘膜，并在第二绝缘膜上形成第三绝缘膜第二绝缘膜。

9. 发明授权

US5604371A Semiconductor device with an insulation film having an end covered by a conductive film 失效
标题翻译：具有绝缘膜的半导体器件，其端部被导电膜覆盖
公开(公告)号：US5604371A
公开(公告)日：1997-02-18
申请号：US421795
申请日：1995-04-14
申请人： Koji Kimura , Yuichi Nakashima , Hiroshi Kawamoto
发明人： Koji Kimura , Yuichi Nakashima , Hiroshi Kawamoto
IPC分类号： H01L21/768 , H01L21/8249 , H01L29/41
CPC分类号： H01L21/8249 , H01L21/76895
摘要： In a semiconductor device, a first conductive film made of, for example, polysilicon is formed on the element region of the semiconductor substrate. An insulation film is formed on the semiconductor substrate, for covering at least the first conductive film. A second conductive film covers at least the end portion of the insulation film. The first conductive film is used as a gate electrode of the MOS transistor, and the second conductive film is used as a protection film for covering and protecting the end portion of the insulation film and a lead-out electrode of the bipolar transistor. The end portion of the insulation film is covered and protected by the second conductive film obtained by patterning the conductive layer made of, for example, polysilicon. Further, the conductive layer is patterned so that stepped portions formed on the insulation film and the end portion of the insulation film are covered, and using this pattern, anisotropic etching is carried out. Thus, formation of residue on the side-wall of the second conductive film, on the stepped portions formed as covering the first conductive film, can be avoided. In a later step, the pattern of the second conductive film which covers the stepped portion is removed by etching.
摘要翻译：在半导体器件中，在半导体衬底的元件区域上形成由例如多晶硅制成的第一导电膜。绝缘膜形成在半导体衬底上，用于至少覆盖第一导电膜。第二导电膜至少覆盖绝缘膜的端部。第一导电膜用作MOS晶体管的栅电极，第二导电膜用作覆盖和保护绝缘膜的端部和双极晶体管的引出电极的保护膜。绝缘膜的端部由通过图案化例如由多晶硅制成的导电层获得的第二导电膜覆盖和保护。此外，导电层被图案化，使得形成在绝缘膜上的阶梯部分和绝缘膜的端部被覆盖，并且使用该图案进行各向异性蚀刻。因此，可以避免在形成为覆盖第一导电膜的阶梯部分上在第二导电膜的侧壁上形成残留物。在后续步骤中，通过蚀刻去除覆盖阶梯部分的第二导电膜的图案。

10. 发明授权

US07268434B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07268434B2
公开(公告)日：2007-09-11
申请号：US11397707
申请日：2006-04-05
申请人： Yuichi Nakashima
发明人： Yuichi Nakashima
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/7681 , H01L21/76831 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： There is disclosed a semiconductor device comprising at least one first insulating film provided above a substrate, being formed with at least one first recess having a first width, and being formed with at least one second recess having a second width which is 1/x (x: positive numbers larger than 1) a size of the first width and having a same depth as the first recess, a second insulating film provided at both sides of the first recess and at a lower part of the second recess, and a conductor provided inside of the second insulating films provided at the both sides of the first recess with extending from an opening of the first recess to a bottom surface thereof, and provided with extending from an opening of the second recess to an upper surface of the second insulating film provided at the lower part of the second recess.
摘要翻译：公开了一种半导体器件，其包括设置在衬底上方的至少一个第一绝缘膜，形成有至少一个具有第一宽度的第一凹部，并且形成有至少一个具有第二宽度的第二凹槽，该第二凹槽为1 / x（ x：大于1的正数）第一宽度的尺寸并且具有与第一凹部相同的深度;第二绝缘膜，设置在第一凹部的两侧和第二凹部的下部;以及导体，设置在第一凹部的两侧的第二绝缘膜的内部从第一凹部的开口延伸到其底表面，并且设置有从第二凹部的开口延伸到第二绝缘膜的上表面设置在第二凹部的下部。

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