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1. 发明授权

US5654561A Insulated gate bipolar transistor with multiple buffer layers 失效
标题翻译：具有多个缓冲层的绝缘栅双极晶体管
公开(公告)号：US5654561A
公开(公告)日：1997-08-05
申请号：US562002
申请日：1995-11-22
申请人： Kiyoto Watabe
发明人： Kiyoto Watabe
IPC分类号： H01L29/73 , H01L21/331 , H01L27/06 , H01L29/08 , H01L29/732 , H01L29/739 , H01L29/78 , H01L29/786 , H01L29/74 , H01L27/082 , H01L31/111
CPC分类号： H01L29/7394 , H01L27/0623 , H01L29/0834 , H01L29/7393
摘要： A high-concentration n-type buffer layer and a low-concentration n-type buffer layer are provided between a p-type collector layer and a high-resistance n-type base layer, and respective impurity concentrations of the low-concentration n-type buffer layer and the high-concentration n-type buffer layer are set so that concentrations of carriers that propagate through the low-concentration n-type buffer layer and the high-concentration n-type buffer layer are in excess of the respective impurity concentrations thereof in an ON state. Thus, an insulated gate bipolar transistor having excellent withstand voltage, ON-state voltage and turn-off characteristics is obtained.
摘要翻译：在p型集电极层和高电阻n型基极层之间设置高浓度n型缓冲层和低浓度n型缓冲层，低浓度n型缓冲层的低浓度n型缓冲层，缓冲层和高浓度n型缓冲层的设定使得通过低浓度n型缓冲层和高浓度n型缓冲层传播的载流子浓度超过各自的杂质浓度其处于ON状态。因此，获得具有优异的耐压，导通电压和关断特性的绝缘栅双极晶体管。

2. 发明授权

US4977105A Method for manufacturing interconnection structure in semiconductor device 失效
标题翻译：制造半导体器件互连结构的方法
公开(公告)号：US4977105A
公开(公告)日：1990-12-11
申请号：US391309
申请日：1989-08-09
申请人： Tatsuo Okamoto , Hideo Kotani , Takio Oono , Kiyoto Watabe , Yasushi Kinoshita , Yoshikazu Nishikawa
发明人： Tatsuo Okamoto , Hideo Kotani , Takio Oono , Kiyoto Watabe , Yasushi Kinoshita , Yoshikazu Nishikawa
IPC分类号： H01L23/485 , H01L23/522
CPC分类号： H01L24/02 , H01L21/76805 , H01L23/5226 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01074 , H01L2924/014 , H01L2924/05042
摘要： Conductive layers (5a, 8a) included in a multi-layer structure (30a) are electrically interconnected through an conductive connection wall (13a) provided in a contact hole (12) and contacting the side surface (22) of the multi-layer structure (30a). The upper conductive layer (11a) existing on the multi-layer structure (30a) and the lower conductive layer (3) existing under the multi-layer structure (30a) are electrically interconnected through a conductive film (11b) provided in the contact hole (12). These two interconnections are insulated from each other by an insulating film (18) provided on the connection wall (13a).
摘要翻译：包含在多层结构（30a）中的导电层（5a，8a）通过设置在接触孔（12）中并与多层结构（30a）的侧表面（22）接触的导电连接壁（30a）。存在于多层结构（30a）上的上导电层（11a）和存在于多层结构（30a）下方的下导电层（3）通过设置在接触孔中的导电膜（11b）电连接（12）。这两个互连通过设置在连接壁（13a）上的绝缘膜（18）彼此绝缘。

3. 发明授权

US06531894B2 Pulse generation circuit and a drive circuit 有权
标题翻译：脉冲发生电路和驱动电路
公开(公告)号：US06531894B2
公开(公告)日：2003-03-11
申请号：US09754062
申请日：2001-01-05
申请人： Kiyoto Watabe
发明人： Kiyoto Watabe
IPC分类号： H03K190175
CPC分类号： H03K17/08128 , H03K17/063
摘要： A pulse generation circuit which can be controlled to generate on-signals and off-signals simultaneously for use in testing the protection circuit of a power device's drive circuitry. The protection circuit prevents faulty operation due to dv/dt transient signals which can cause the S and R input signals to a set-reset flip-flop circuit to simultaneously be HI, resulting in an error condition. Protection circuit 26a has the structure as shown in FIG. 1. A pulse generation circuit, as shown in FIG. 3, can be used to provide simultaneous changes of logic value at B and C to test the protection circuit.
摘要翻译：脉冲发生电路，其可以被控制以同时产生信号和关闭信号，以用于测试功率器件的驱动电路的保护电路。保护电路可以防止由于dv / dt瞬态信号导致的故障操作，这可能导致S和R输入信号到设置复位触发器电路同时为HI，导致错误状况。保护电路26a具有如图1所示的结构。脉冲发生电路，如图1所示。 3，可以在B和C上同时提供逻辑值的变化来测试保护电路。

4. 发明授权

US5753957A Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5753957A
公开(公告)日：1998-05-19
申请号：US803112
申请日：1997-02-20
申请人： Kiyoto Watabe
发明人： Kiyoto Watabe
IPC分类号： H01L27/06 , H01L21/331 , H01L21/8249 , H01L29/73 , H01L29/732 , H01L29/76
CPC分类号： H01L21/8249 , H01L27/0623 , Y10S148/009 , Y10S257/90
摘要： The present invention is mainly characterized in that a Bi-CMOS is obtained in which characteristics of a bipolar transistor are not deteriorated. The device includes a bipolar transistor and a CMOSFET formed on a semiconductor substrate separately from each other by a field oxide film. The thickness of a gate electrode of an NMOSFET and a gate electrode of a PMOSFET is made larger than the thickness of an emitter electrode of the bipolar transistor.
摘要翻译：本发明的主要特征在于获得双极晶体管的特性不劣化的Bi-CMOS。该器件包括通过场氧化膜彼此分开形成在半导体衬底上的双极晶体管和CMOSFET。 NMOSFET的栅电极和PMOSFET的栅电极的厚度大于双极晶体管的发射极的厚度。

5. 发明授权

US5559348A Semiconductor device having insulated gate bipolar transistor 失效
标题翻译：具有绝缘栅双极晶体管的半导体器件
公开(公告)号：US5559348A
公开(公告)日：1996-09-24
申请号：US460942
申请日：1995-06-05
申请人： Kiyoto Watabe , Ikunori Takata , Masana Harada
发明人： Kiyoto Watabe , Ikunori Takata , Masana Harada
IPC分类号： H01L29/78 , H01L29/06 , H01L29/739 , H01L29/786 , H01L29/74 , H01L23/58 , H01L27/01
CPC分类号： H01L29/0619 , H01L29/7394 , H01L29/7398 , H01L2924/0002
摘要： A semiconductor device which allows an ON-state voltage to be lower than that of a conventional device and a method of manufacturing such a device. In this semiconductor device, a gate electrode is formed to have a planar area of its region covering a first base layer larger than that of its region covering a second base layer, thereby increasing a cathode short-circuit ratio of a cathode-shorted diode equivalent to this semiconductor device. As a result, a lower voltage than conventional ON-state can be obtained.
摘要翻译：允许ON状态电压低于常规器件的半导体器件和制造这种器件的方法。在该半导体装置中，栅电极形成为具有覆盖比覆盖第二基极层的区域大的第一基极层的区域的平面区域，由此增加阴极短路二极管等效电极的阴极短路比到该半导体器件。结果，可以获得比常规ON状态更低的电压。

6. 发明授权

US5541440A Isolation structure for semiconductor device 失效
标题翻译：半导体器件隔离结构
公开(公告)号：US5541440A
公开(公告)日：1996-07-30
申请号：US278289
申请日：1994-07-21
申请人： Yutaka Kozai , Kiyoto Watabe , Tatsuhiko Ikeda
发明人： Yutaka Kozai , Kiyoto Watabe , Tatsuhiko Ikeda
IPC分类号： H01L21/76 , H01L21/763 , H01L21/8249 , H01L27/06 , H01L29/06 , H01L29/00
CPC分类号： H01L29/0649 , H01L21/763
摘要： It is an object of the present invention to provide a semiconductor device which has a high electrical isolation capability and an enhanced electrical reliability for avoiding short circuit of individual conductive layers, and the present invention also provides a method of manufacturing such a semiconductor device. An n.sup.+ buried layer and an n.sup.- epitaxial growth layer are formed on a p.sup.- silicon substrate. An element isolation oxide film having a through hole is formed on the surface of n.sup.- epitaxial growth layer. A trench which penetrates through n.sup.- epitaxial growth layer and n.sup.+ buried layer to reach a predetermined depth of p.sup.- silicon substrate is formed under through hole. A first insulating layer covers the internal wall of trench. A covering layer covers the sidewall of through hole. A filling layer is formed to fill trench so that the top surface thereof is located within through hole. A second insulating layer is formed on filling layer.
摘要翻译：本发明的目的是提供一种半导体器件，其具有高的隔离能力和增强的电可靠性，以避免各个导电层的短路，并且本发明还提供一种制造这种半导体器件的方法。在p-硅衬底上形成n +掩埋层和n-外延生长层。在n外延生长层的表面上形成具有通孔的元件隔离氧化膜。在通孔下面形成穿过n外延生长层和n +掩埋层达到p硅衬底的预定深度的沟槽。第一绝缘层覆盖沟槽的内壁。覆盖层覆盖通孔的侧壁。形成填充层以填充沟槽，使得其顶表面位于通孔内。在填充层上形成第二绝缘层。

7. 发明授权

US5869377A Method of fabrication LDD semiconductor device with amorphous regions 失效
标题翻译：制造具有非晶区域的LDD半导体器件的方法
公开(公告)号：US5869377A
公开(公告)日：1999-02-09
申请号：US193912
申请日：1994-02-03
申请人： Kiyoto Watabe , Satoru Kamoto
发明人： Kiyoto Watabe , Satoru Kamoto
IPC分类号： H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28105 , H01L29/4983 , H01L29/6656 , H01L29/78 , H01L29/7836 , Y10S148/106
摘要： A method of fabricating a MOS field effect semiconductor device having an LDD structure is described in which an insulating film is formed on a gate electrode and a layer of polycrystalline silicon, oxide, high melting point metal or a silicide of a high melting point metal is formed on a wafer and etched away by anisotropic RIE, except a portion thereof on a sidewall of the gate. With the resulting structure, degradation of the transconductance of the device due to injection of hot carriers is prevented. Also, the size of the device can be minimized without unduly increasing the resistances of the drain/source region, the gate electrode, and the contacts of the device.
摘要翻译：描述了一种制造具有LDD结构的MOS场效应半导体器件的方法，其中在栅电极上形成绝缘膜，并且多晶硅，氧化物，高熔点金属或高熔点金属的硅化物层是形成在晶片上并且通过各向异性RIE蚀刻除去栅极侧壁上的一部分。利用所得到的结构，防止了由于热载体的注入引起的器件跨导的劣化。此外，可以最小化器件的尺寸，而不会过度增加漏极/源极区域，栅极电极和器件的触点的电阻。

8. 发明授权

US4872050A Interconnection structure in semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件的互连结构及其制造方法
公开(公告)号：US4872050A
公开(公告)日：1989-10-03
申请号：US168386
申请日：1988-03-15
申请人： Tatsuo Okamoto , Hideo Kotani , Takio Oono , Kiyoto Watabe , Yasushi Kinoshita , Yoshikazu Nishikawa
发明人： Tatsuo Okamoto , Hideo Kotani , Takio Oono , Kiyoto Watabe , Yasushi Kinoshita , Yoshikazu Nishikawa
IPC分类号： H01L23/485 , H01L23/522
CPC分类号： H01L24/02 , H01L21/76805 , H01L23/5226 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01074 , H01L2924/014 , H01L2924/05042
摘要： Conductive layers (5a, 9a) included in a multi-layer structure (30a) are electrically interconnected through a conductive connection wall (13a) provided in a contact hole (12) and contacting the side surface (22) of the multi-layer structure (30a). The upper conductive layer (11a) existing on the multi-layer structure (30a) and the lower conductive layer (3) exisitng under the multi-layer structure (30a) are electrically interconnected through a conductive film (11b) provided in the contact hole (12). These two interconnections are insulated from each other by an insulating film (18) provided on the connection wall (13a).
摘要翻译：包含在多层结构（30a）中的导电层（5a，9a）通过设置在接触孔（12）中并与多层结构（30a）的侧表面（22）接触的导电连接壁（30a）。存在于层叠结构体（30a）的多层结构（30a）和下导电层（3）上的上导电层（11a）通过设置在接触孔中的导电膜（11b）电连接（12）。这两个互连通过设置在连接壁（13a）上的绝缘膜（18）彼此绝缘。

9. 发明授权

US06664822B2 Driving device having dummy circuit 有权
标题翻译：具有虚拟电路的驱动装置
公开(公告)号：US06664822B2
公开(公告)日：2003-12-16
申请号：US10265685
申请日：2002-10-08
申请人： Kiyoto Watabe
发明人： Kiyoto Watabe
IPC分类号： H03B100
CPC分类号： H03K17/063 , H02M7/538 , H03K17/168 , H03K17/567 , H03K17/6871
摘要： A dummy circuit (303) is basically configured in the same manner as level shift circuits (203a, 203b), but an HVNMOS (311) of the dummy circuit is always set at a non-conducting state. A mask circuit (403) removes noise in signals (S200a, S200b) outputted from the level shift circuits (203a, 203b), respectively, using a signal (S300) outputted from the dummy circuit (303). Control signals (S100a, S100b) include iterative pulses that are transmitted to S and R inputs of an RS flip-flop (502). PMOSs (215, 225) bring current paths (210, 220) into a non-conducting state in response to an output signal (S500) from the RS flip-flop (502) to thereby suspend one of the level shift circuits (203a, 203b).
摘要翻译：虚拟电路（303）基本上以与电平移位电路（203a，203b）相同的方式构成，但虚设电路的HVNMOS（311）总是设定在非导通状态。掩模电路（403）使用从虚拟电路（303）输出的信号（S300）分别去除从电平移位电路（203a，203b）输出的信号（S200a，S200b）中的噪声。控制信号（S100a，S100b）包括发送到RS触发器（502）的S和R输入的迭代脉冲。响应于来自RS触发器（502）的输出信号（S500），PMOS（215,225）使电流路径（210,220）进入非导通状态，从而暂停电平移位电路（203a， 203b）。

10. 发明授权

US06198130B1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06198130B1
公开(公告)日：2001-03-06
申请号：US09003338
申请日：1998-01-06
申请人： Shinji Nobuto , Kiyoto Watabe , Hideki Takahashi
发明人： Shinji Nobuto , Kiyoto Watabe , Hideki Takahashi
IPC分类号： H01L2976
CPC分类号： H01L29/7824 , H01L29/0696 , H01L29/4232 , H01L29/4238 , H01L29/7394
摘要： An ON-state voltage is reduced. A line of gate trenches 8 is formed on an n-type silicon layer (a SOI layer) 3 so as to divide a p-type base layer 4 and an n-type emitter layer 5. The gate trench 8 extends from the n-type emitter layer 5 toward a collector electrode 21. A gate electrode 10 is buried in the gate trench 8 with a gate insulation film 9 interposed therebetween. The gate electrode 10 is provided opposite to a vertical section of the p-type base layer 4. Therefore, a channel width can be kept great. Furthermore, a wide region of the n-type silicon layer 3 which is provided opposite to the gate trench 8 functions as an accumulation layer of a hole. As a result, the ON-state voltage can be reduced.
摘要翻译： ON状态电压降低。在n型硅层（SOI层）3上形成一个栅极沟槽8，以分隔p型基极层4和n型发射极层5.栅极沟槽8从n- 型发射极层5朝向集电极21.栅极10埋设在栅沟槽8中，栅极绝缘膜9插入其间。栅电极10设置成与p型基极层4的垂直部分相对。因此，沟道宽度可以保持很大。此外，与栅沟槽8相对设置的n型硅层3的宽区域用作孔的堆积层。结果，可以降低导通电压。

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