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1. 发明授权

US07491344B2 Method for etching an object using a plasma and an object etched by a plasma 有权
标题翻译：使用等离子体蚀刻物体的方法和由等离子体蚀刻的物体
公开(公告)号：US07491344B2
公开(公告)日：2009-02-17
申请号：US10703947
申请日：2003-11-04
申请人： Heung-Sik Park , Chang-Jin Kang , Tae-Hyuk Ahn , Kyeong-Koo Chi , Sang-Hun Seo
发明人： Heung-Sik Park , Chang-Jin Kang , Tae-Hyuk Ahn , Kyeong-Koo Chi , Sang-Hun Seo
IPC分类号： C23F1/00
CPC分类号： H01J37/32055 , H01L21/3065 , H01L21/78 , H05H1/44
摘要： Disclosed herein is a method for etching a face of an object and more particularly a method for etching a rear face of a silicon substrate. The object having a silicon face is positioned so as to be spaced apart from a plasma-generating member by a predetermined interval distance. The plasma-generating member generates arc plasmas to form a plasma region. A reaction gas is allowed to pass through the plasma region to generate radicals having high energies and high densities. The radicals react with the object to etch the face of the object. The face of the object can be rapidly and uniformly etched.
摘要翻译：本文公开了一种用于蚀刻物体的表面的方法，更具体地，蚀刻硅衬底的背面的方法。具有硅面的物体被定位成与等离子体产生构件间隔预定间隔距离。等离子体产生部件产生电弧等离子体以形成等离子体区域。允许反应气体通过等离子体区域以产生具有高能量和高密度的自由基。自由基与物体反应以蚀刻物体的表面。物体的表面可以快速均匀地蚀刻。

2. 发明申请

US20060024932A1 Methods of forming semiconductor devices including removing a thickness of a polysilicon gate layer 审中-公开
标题翻译：形成半导体器件的方法包括去除多晶硅栅极层的厚度
公开(公告)号：US20060024932A1
公开(公告)日：2006-02-02
申请号：US11191488
申请日：2005-07-28
申请人： Heung-Sik Park , Kyeong-Koo Chi , Chang-Jin Kang
发明人： Heung-Sik Park , Kyeong-Koo Chi , Chang-Jin Kang
IPC分类号： H01L21/425
CPC分类号： H01L21/823842
摘要： Embodiments of the present invention provide methods of forming a semiconductor device including forming a polysilicon layer on a semiconductor substrate and doping the polysilicon layer with P-type impurities. The semiconductor substrate including the polysilicon layer is annealed and then an upper portion having a first thickness of the annealed polysilicon layer doped with the P-type impurities is removed. The first thickness is selected to remove defects formed in the polysilicon layer during doping and/or annealing thereof.
摘要翻译：本发明的实施例提供了形成半导体器件的方法，该半导体器件包括在半导体衬底上形成多晶硅层，并用P型杂质掺杂多晶硅层。包括多晶硅层的半导体衬底被退火，然后去除掺杂有P型杂质的退火多晶硅层的第一厚度的上部。选择第一厚度以去除在其掺杂和/或退火期间在多晶硅层中形成的缺陷。

3. 发明申请

US20070020565A1 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070020565A1
公开(公告)日：2007-01-25
申请号：US11429071
申请日：2006-05-08
申请人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
发明人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
IPC分类号： G03F7/26
CPC分类号： G03F7/0035 , G03F7/40 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern. The second hard mask layer may be anisotropically etched using the first etch mask pattern and/or the buffer layer pattern as etch masks, forming a second hard mask pattern. The first hard mask layer may be anisotropically etched using the second hard mask pattern as an etch mask, forming a first hard mask pattern. The etched layer may be anisotropically etched using the first hard mask pattern as an etch mask.
摘要翻译：提供制造半导体器件的方法。还提供了使用缓冲层来形成更精细图案的半导体器件的方法，该缓冲层用于通过双重图案化来形成更精细图案的低于分辨率极限的光刻工艺的图案之间桥接形成。可以在要蚀刻的基板的层上形成第一硬掩模层和/或第二硬掩模层。可以在第二硬掩模层上形成第一间距的第一蚀刻掩模图案。在衬底的整个表面上形成缓冲层之后，可以在第一蚀刻掩模图案之间的区域中形成第二间距的第二蚀刻掩模图案。可以使用第二蚀刻掩模图案作为蚀刻掩模来各向异性地蚀刻缓冲层，形成缓冲层图案。可以使用第一蚀刻掩模图案和/或缓冲层图案作为蚀刻掩模对第二硬掩模层进行各向异性蚀刻，形成第二硬掩模图案。可以使用第二硬掩模图案作为蚀刻掩模对第一硬掩模层进行各向异性蚀刻，形成第一硬掩模图案。蚀刻层可以使用第一硬掩模图案作为蚀刻掩模进行各向异性蚀刻。

4. 发明授权

US07540970B2 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07540970B2
公开(公告)日：2009-06-02
申请号：US11429071
申请日：2006-05-08
申请人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
发明人： Cha-Won Koh , Sang-Gyun Woo , Jeong-Lim Nam , Kyeong-Koo Chi , Seok-Hwan Oh , Gi-Sung Yeo , Seung-Pil Chung , Heung-Sik Park
IPC分类号： C03C15/00
CPC分类号： G03F7/0035 , G03F7/40 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： Methods of fabricating a semiconductor device are provided. Methods of forming a finer pattern of a semiconductor device using a buffer layer for retarding, or preventing, bridge formation between patterns in the formation of a finer pattern below resolution limits of a photolithography process by double patterning are also provided. A first hard mask layer and/or a second hard mask layer may be formed on a layer of a substrate to be etched. A first etch mask pattern of a first pitch may be formed on the second hard mask layer. After a buffer layer is formed on the overall surface of the substrate, a second etch mask pattern of a second pitch may be formed thereon in a region between the first etch mask pattern. The buffer layer may be anisotropically etched using the second etch mask pattern as an etch mask, forming a buffer layer pattern. The second hard mask layer may be anisotropically etched using the first etch mask pattern and/or the buffer layer pattern as etch masks, forming a second hard mask pattern. The first hard mask layer may be anisotropically etched using the second hard mask pattern as an etch mask, forming a first hard mask pattern. The etched layer may be anisotropically etched using the first hard mask pattern as an etch mask.
摘要翻译：提供制造半导体器件的方法。还提供了使用缓冲层来形成更精细图案的半导体器件的方法，该缓冲层用于通过双重图案化来形成更精细图案的低于分辨率极限的光刻工艺的图案之间桥接形成。可以在要蚀刻的基板的层上形成第一硬掩模层和/或第二硬掩模层。可以在第二硬掩模层上形成第一间距的第一蚀刻掩模图案。在衬底的整个表面上形成缓冲层之后，可以在第一蚀刻掩模图案之间的区域中形成第二间距的第二蚀刻掩模图案。可以使用第二蚀刻掩模图案作为蚀刻掩模来各向异性地蚀刻缓冲层，形成缓冲层图案。可以使用第一蚀刻掩模图案和/或缓冲层图案作为蚀刻掩模对第二硬掩模层进行各向异性蚀刻，形成第二硬掩模图案。可以使用第二硬掩模图案作为蚀刻掩模对第一硬掩模层进行各向异性蚀刻，形成第一硬掩模图案。蚀刻层可以使用第一硬掩模图案作为蚀刻掩模进行各向异性蚀刻。

5. 发明授权

US06534921B1 Method for removing residual metal-containing polymer material and ion implanted photoresist in atmospheric downstream plasma jet system 有权
标题翻译：用于在大气下游等离子体喷射系统中去除残留金属的聚合物材料和离子注入的光致抗蚀剂的方法
公开(公告)号：US06534921B1
公开(公告)日：2003-03-18
申请号：US09708737
申请日：2000-11-09
申请人： Sang-Hun Seo , Kyeong-Koo Chi , Ji-Soo Kim , Chang-Woong Chu , Seung-Pil Chung
发明人： Sang-Hun Seo , Kyeong-Koo Chi , Ji-Soo Kim , Chang-Woong Chu , Seung-Pil Chung
IPC分类号： H01J724
CPC分类号： H01L21/31138 , B08B7/0035 , G03F7/427 , H05H1/44
摘要： A method of removing metal-containing polymeric material and ion implanted or plasma damaged photoresist from a surface using a plasma jet system, by generating radicals having high energy and high density from atmospheric plasma by introducing a reactant gas to the plasma, and placing the surface at a distance from the plasma, whereby ionic reaction on the surface is minimized while the removing action of the radicals on the surface is maintained.
摘要翻译：通过使用等离子体喷射系统从表面去除含金属的聚合物材料和离子注入或等离子体损伤的光致抗蚀剂的方法，通过向等离子体引入反应气体，通过从等离子体引入具有高能量和高密度的自由基，并将表面距离等离子体一定距离，由此表面上的离子反应被最小化，同时维持表面上的自由基的去除作用。

6. 发明申请

US20050158948A1 Semiconductor device having self-aligned contact plug and method for fabricating the same 有权
公开(公告)号：US20050158948A1
公开(公告)日：2005-07-21
申请号：US11058670
申请日：2005-02-15
申请人： Myeong-Cheol Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Young Son
发明人： Myeong-Cheol Kim , Chang-Jin Kang , Kyeong-Koo Chi , Seung-Young Son
IPC分类号： H01L21/28 , H01L21/60 , H01L21/8242 , H01L23/522 , H01L27/108
CPC分类号： H01L21/76831 , H01L21/76897 , H01L23/5226 , H01L27/10814 , H01L27/10855 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device having a self-aligned contact plug and a method of fabricating the semiconductor device. The semiconductor device includes conductive patterns, a first interlayer insulating layer, a first spacer, a second interlayer insulating layer, and a contact plug. In each conductive pattern, a conductive layer and a capping layer are sequentially deposited on an insulating layer over a semiconductor substrate. The first interlayer insulating layer fills spaces between the conductive patterns and has a height such that when the first interlayer insulating layer is placed on the insulating layer, the first interlayer insulating layer is lower than a top surface of the capping layer but higher than a top surface of the conductive layer. The first spacer surrounds the outer surface of the capping layer on the first interlayer insulating layer. The second interlayer insulating layer covers the first interlayer insulating layer, the capping layer, and the first spacer and has a planarized top surface. The contact plug passes through the second interlayer insulating layer, the first interlayer insulating layer, and the insulating layer between the conductive patterns, is electrically connected to the semiconductor substrate, has an outerwall surrounded by a second spacer, and is self-aligned with the capping layer.

7. 发明申请

US20050130371A1 Method of fabricating semiconductor device having capacitor 有权
公开(公告)号：US20050130371A1
公开(公告)日：2005-06-16
申请号：US11048995
申请日：2005-02-02
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/3213
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

8. 发明授权

US06867096B2 Method of fabricating semiconductor device having capacitor 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US06867096B2
公开(公告)日：2005-03-15
申请号：US10855165
申请日：2004-05-27
申请人： Sung-IL Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-IL Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/314 , H01L21/316 , H01L21/3213
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层电极在下电极上。

9. 发明授权

US08941165B2 Methods of fabricating integrated circuit capacitors having u-shaped lower capacitor electrodes 有权
标题翻译：制造具有u形下电容器电极的集成电路电容器的方法
公开(公告)号：US08941165B2
公开(公告)日：2015-01-27
申请号：US12779300
申请日：2010-05-13
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L27/108 , H01L49/02 , H01L21/3213 , H01L21/314 , H01L21/316
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层电极在下电极上。

10. 发明授权

US07709346B2 Semiconductor device with trench gate type transistor and method of manufacturing the same 有权
标题翻译：具有沟槽栅型晶体管的半导体器件及其制造方法
公开(公告)号：US07709346B2
公开(公告)日：2010-05-04
申请号：US11624905
申请日：2007-01-19
申请人： Yong-Jin Kim , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Mybong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
发明人： Yong-Jin Kim , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Mybong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
IPC分类号： H01L21/76
CPC分类号： H01L29/66621 , H01L21/823437 , H01L27/10876 , H01L29/7834
摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.
摘要翻译：半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁，活动区域延伸的第二方向。隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

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