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1. 发明授权

US07725860B1 Contact mapping using channel routing 有权
标题翻译：使用通道路由联系映射
公开(公告)号：US07725860B1
公开(公告)日：2010-05-25
申请号：US10728894
申请日：2003-12-08
申请人： Herman Kwong , Kah Ming Soh , Martin Handforth , Larry Marcanti
发明人： Herman Kwong , Kah Ming Soh , Martin Handforth , Larry Marcanti
IPC分类号： G06F17/50 , H05K3/02
CPC分类号： H05K3/0005 , H05K1/0286 , H05K1/0298 , H05K2201/10212 , H05K2201/10689 , Y10T29/49155 , Y10T29/49156
摘要： A technique for improved mapping of the contacts of a PLD to the contacts of one or more other electronic components are provided. In one particular exemplary embodiment, the technique may be realized as a method for mapping contacts of a programmable logic device (PLD) to an electronic component in a signal routing device having one or more layers. The method comprises assigning a set of one or more contacts of the PLD to one or more respective contacts of the electronic component based at least in part on a pattern of electrically conductive traces routed from respective contacts of the electronic component via one or more channels formed at one or more layers of the signal routing device.
摘要翻译：提供了一种用于改进PLD的触点与一个或多个其它电子部件的触点的映射的技术。在一个特定示例性实施例中，该技术可以被实现为用于将可编程逻辑器件（PLD）的触点映射到具有一个或多个层的信号路由设备中的电子部件的方法。该方法包括至少部分地基于经由形成的一个或多个通道从电子部件的相应触点路由的导电迹线的图案，将一组PLD的一个或多个触点分配给电子部件的一个或多个相应的触点在信号路由设备的一层或多层。

2. 发明授权

US07204018B2 Technique for reducing via capacitance 有权
标题翻译：降低通孔电容的技术
公开(公告)号：US07204018B2
公开(公告)日：2007-04-17
申请号：US11012127
申请日：2004-12-16
申请人： Herman Kwong , Larry Marcanti , Aneta Wyrzykowska , Kah Ming Soh
发明人： Herman Kwong , Larry Marcanti , Aneta Wyrzykowska , Kah Ming Soh
IPC分类号： H01L23/48 , H01K3/10 , H03H7/38
CPC分类号： H05K3/403 , H05K1/115 , H05K3/0032 , H05K3/0044 , H05K3/045 , H05K3/107 , H05K3/1258 , H05K3/4069 , H05K3/429 , H05K2201/09645 , H05K2201/09854 , H05K2203/1476 , Y10T29/49016 , Y10T29/49139 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A technique for reducing via capacitance is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for reducing via capacitance. The method may comprise forming, in a circuit board, a via hole that bridges a first trace and a second trace. The method may also comprise forming a channel in a sidewall of the via hole. The method may further comprise filling the via hole and the channel with a conductive material. The method may additionally comprise removing the conductive material from the via hole without depleting the channel, thereby forming an interconnect that couples the first trace to the second trace.
摘要翻译：公开了一种降低通孔电容的技术。在一个特定的示例性实施例中，该技术可以被实现为用于减小通孔电容的方法。该方法可以包括在电路板中形成桥接第一迹线和第二迹线的通孔。该方法还可以包括在通孔的侧壁中形成通道。该方法还可以包括用导电材料填充通孔和通道。该方法可以另外包括从通孔去除导电材料而不耗尽通道，从而形成将第一迹线耦合到第二迹线的互连。

3. 发明授权

US07281326B1 Technique for routing conductive traces between a plurality of electronic components of a multilayer signal routing device 有权
标题翻译：用于在多层信号路由设备的多个电子部件之间布线导电迹线的技术
公开(公告)号：US07281326B1
公开(公告)日：2007-10-16
申请号：US10728881
申请日：2003-12-08
申请人： Herman Kwong , Aneta Wyrzykowska , Kah Ming Soh , Eileen Goulet , Luigi Difilippo , Larry Marcanti
发明人： Herman Kwong , Aneta Wyrzykowska , Kah Ming Soh , Eileen Goulet , Luigi Difilippo , Larry Marcanti
IPC分类号： H01K3/10
CPC分类号： H05K1/181 , H01L2224/16225 , H05K1/0298 , H05K1/112 , H05K2201/09227 , H05K2201/10734 , Y02P70/611 , Y10T29/49117 , Y10T29/49155 , Y10T29/49165
摘要： Techniques for reducing the number of layers in a multilayer signal routing device are disclosed. The technique may be realized as a method for routing one or more conductive traces between a plurality of electronic components of a multilayer signal routing device. The method comprises forming a first inter-component channel at a first routing layer of the multilayer signal routing device, the first inter-component channel extending between a first set of two or more electronic components of the plurality of electronic components and having a first orientation and forming a second inter-component channel at a second routing layer of the multilayer signal routing device, the second inter-component channel extending between a second set of two or more electronic components of the plurality of electronic components and having a second orientation different from the first orientation.
摘要翻译：公开了用于减少多层信号路由设备中的层数的技术。该技术可以被实现为用于在多层信号路由设备的多个电子部件之间路由一个或多个导电迹线的方法。该方法包括在多层信号路由设备的第一路由层处形成第一分组间信道，第一分组间信道在多个电子部件的第一组两个或多个电子部件之间延伸并具有第一取向以及在所述多层信号路由设备的第二路由层处形成第二组件间通道，所述第二组件间通道在所述多个电子部件的第二组两个或更多个电子部件之间延伸，并且具有不同于第一个方向。

4. 发明授权

US06975517B1 Embedded preemphasis and deemphasis circuits 有权
标题翻译：嵌入式预加重和去加重电路
公开(公告)号：US06975517B1
公开(公告)日：2005-12-13
申请号：US10448227
申请日：2003-05-30
申请人： Herman Kwong , Kah Ming Soh , Larry Marcanti
发明人： Herman Kwong , Kah Ming Soh , Larry Marcanti
IPC分类号： H05K1/00 , H05K1/02 , H05K1/16 , H05K1/18
CPC分类号： H05K1/16 , H05K1/0216 , H05K1/0298 , H05K1/162 , H05K1/167 , H05K2201/09672 , H05K2201/1006
摘要： Exemplary techniques for providing an embedded preemphasis circuit and/or a deemphasis circuit in a printed circuit board (PCB) or other circuit device are disclosed. In particular, a technique for preemphasizing and/or deemphasizing transmitted signals in a PCB-based circuit is provided. The technique may be realized as a preemphasis circuit for preemphasizing a signal being transmitted from a signal source to a signal destination. The preemphasis circuit comprises a printed circuit board (PCB), a resistor embedded in the PCB and having a first terminal electrically connected to the signal source and a second terminal electrically connected to the signal destination, and a capacitor embedded in the PCB and having a first terminal electrically connected to the signal source and a second terminal electrically connected to the signal destination.
摘要翻译：公开了用于在印刷电路板（PCB）或其它电路装置中提供嵌入式预加重电路和/或去加重电路的示例性技术。特别地，提供了一种用于在基于PCB的电路中预加重和/或去加重传输信号的技术。该技术可以被实现为用于预加重从信号源发送到信号目的地的信号的预加重电路。预加重电路包括印刷电路板（PCB），嵌入PCB中的电阻器，并且具有电连接到信号源的第一端子和电连接到信号目的地的第二端子以及嵌入在PCB中的电容器电连接到信号源的第一端子和电连接到信号端的第二端子。

5. 发明授权

US07385470B2 Technique for reducing via capacitance 有权
标题翻译：降低通孔电容的技术
公开(公告)号：US07385470B2
公开(公告)日：2008-06-10
申请号：US11723851
申请日：2007-03-22
申请人： Herman Kwong , Larry Marcanti , Aneta Wyrzykowska , Kah Ming Soh
发明人： Herman Kwong , Larry Marcanti , Aneta Wyrzykowska , Kah Ming Soh
IPC分类号： H03H7/38
CPC分类号： H05K3/403 , H05K1/115 , H05K3/0032 , H05K3/0044 , H05K3/045 , H05K3/107 , H05K3/1258 , H05K3/4069 , H05K3/429 , H05K2201/09645 , H05K2201/09854 , H05K2203/1476 , Y10T29/49016 , Y10T29/49139 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： A technique for reducing via capacitance is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for reducing via capacitance. The method may comprise forming, in a circuit board, a via hole that bridges a first trace and a second trace. The method may also comprise forming a channel in a sidewall of the via hole. The method may further comprise filling the via hole and the channel with a conductive material. The method may additionally comprise removing the conductive material from the via hole without depleting the channel, thereby forming an interconnect that couples the first trace to the second trace.
摘要翻译：公开了一种降低通孔电容的技术。在一个特定的示例性实施例中，该技术可以被实现为用于减小通孔电容的方法。该方法可以包括在电路板中形成桥接第一迹线和第二迹线的通孔。该方法还可以包括在通孔的侧壁中形成通道。该方法还可以包括用导电材料填充通孔和通道。该方法可以另外包括从通孔去除导电材料而不耗尽通道，从而形成将第一迹线耦合到第二迹线的互连。

6. 发明授权

US07813409B2 Secure network using orthogonal frequency division multiplexing spread spectrum communications 有权
标题翻译：使用正交频分复用扩频通信的安全网络
公开(公告)号：US07813409B2
公开(公告)日：2010-10-12
申请号：US11236230
申请日：2005-09-27
申请人： Herman Kwong , Kah Ming Soh , Bryan Parlor , Aneta Wyrzykowska
发明人： Herman Kwong , Kah Ming Soh , Bryan Parlor , Aneta Wyrzykowska
IPC分类号： H04B1/00
CPC分类号： H04L27/2602 , H04L1/0003 , H04L1/0025 , H04L1/0071 , H04L1/1867 , H04L1/22
摘要： Described are a method and system for secure transmission of data through a network. A subcarrier sequence for data transmission is generated. The subcarrier sequence designates at least one subcarrier from a number of orthogonal subcarriers for each of a plurality of intervals in a time sequence. The subcarrier sequence is provided to a receiver. A data signal that includes the subcarriers identified in the subcarrier sequence modulated according to the data is transmitted from a transmitter to the receiver. For additional security, the subcarrier sequence can be transmitted to the receiver using a communications channel that is separate from the communications channel for the data signal. The data signal is detected at the receiver and demodulated according to the subcarrier sequence.
摘要翻译：描述了通过网络安全地传输数据的方法和系统。产生用于数据传输的子载波序列。子载波序列在时间序列中为多个间隔中的每一个指定来自多个正交子载波的至少一个副载波。子载波序列被提供给接收机。包括根据数据调制的子载波序列中识别的子载波的数据信号从发射机发射到接收机。为了额外的安全性，可以使用与用于数据信号的通信信道分开的通信信道将副载波序列发送到接收机。在接收机处检测数据信号，并根据子载波序列进行解调。

7. 发明授权

US07515434B2 Technique for enhancing circuit density and performance 失效
标题翻译：提高电路密度和性能的技术
公开(公告)号：US07515434B2
公开(公告)日：2009-04-07
申请号：US11014962
申请日：2004-12-20
申请人： Aneta Wyrzykowska , Herman Kwong , Kah Ming Soh
发明人： Aneta Wyrzykowska , Herman Kwong , Kah Ming Soh
IPC分类号： H05K1/18
CPC分类号： H05K1/0246 , H01L2224/16225 , H05K1/023 , H05K1/141 , H05K1/16 , H05K1/162 , H05K1/165 , H05K1/167 , H05K1/184 , H05K3/4046 , H05K3/4053 , H05K2201/0187 , H05K2201/10045 , H05K2201/10545 , H05K2201/10636 , H05K2201/10734 , Y02P70/611
摘要： A technique for enhancing circuit density and performance is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for enhancing circuit density and performance of a microelectronic module. The method may comprise forming a discrete package, wherein the discrete package comprises one or more passive devices that are desirable for the performance of the microelectronic module. The method may also comprise coupling the discrete package to the microelectronic module.
摘要翻译：公开了一种用于增强电路密度和性能的技术。在一个特定的示例性实施例中，该技术可以被实现为用于增强微电子模块的电路密度和性能的方法。该方法可以包括形成分立封装，其中分立封装包括对微电子模块执行所期望的一个或多个无源器件。该方法还可以包括将分立封装耦合到微电子模块。

8. 发明授权

US07409020B1 Technique for filter-enhanced clock synchronization 失效
标题翻译：滤波增强时钟同步技术
公开(公告)号：US07409020B1
公开(公告)日：2008-08-05
申请号：US10732532
申请日：2003-12-11
申请人： Aneta Wyrzykowska , Kah Ming Soh , James Aweya , Delfin Montuno , Michel Ouellette
发明人： Aneta Wyrzykowska , Kah Ming Soh , James Aweya , Delfin Montuno , Michel Ouellette
IPC分类号： H04B1/10
CPC分类号： H03L7/093 , H04J3/0632
摘要： A technique for filter-enhanced clock synchronization is disclosed. In one particular exemplary embodiment, the technique may be realized by/as a method for filter-enhanced clock synchronization. The method comprises subjecting a clock error signal to a first exponentially weighted moving average (EWMA) filter to generate a first output signal, where the first EWMA filter comprises a first gain element. And the method further comprises subjecting the first output signal to a second EWMA filter to generate a second output signal, where the second EWMA filter comprises a second gain element and the second EWMA filter is coupled with a feedback loop having a delay element and a summing junction.
摘要翻译：公开了一种用于滤波器增强时钟同步的技术。在一个特定的示例性实施例中，该技术可以通过/作为滤波器增强时钟同步的方法来实现。该方法包括使时钟误差信号经受第一指数加权移动平均（EWMA）滤波器以产生第一输出信号，其中第一EWMA滤波器包括第一增益元件。并且该方法还包括使第一输出信号经受第二EWMA滤波器以产生第二输出信号，其中第二EWMA滤波器包括第二增益元件，而第二EWMA滤波器与具有延迟元件的反馈回路耦合，交界处

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