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1. 发明授权

US4454531A Digital circuit for providing a binary signal on the occurrence of a predetermined frequency ratio of two signals 失效
标题翻译：数字电路，用于在出现两个信号的预定频率比时提供二进制信号
公开(公告)号：US4454531A
公开(公告)日：1984-06-12
申请号：US350556
申请日：1982-02-22
申请人： Herbert Elmis , Adrian Klar
发明人： Herbert Elmis , Adrian Klar
IPC分类号： G01R23/10 , G01R23/15 , H03D13/00 , H04N5/04 , H04N9/44
CPC分类号： H04N9/44
摘要： The invention provides a digital circuit for generating a binary signal output when a predetermined frequency ratio, v=f1/f2, of two signals F1 and F2 occurs during a selected measuring period. The circuit is particularly adapted for use in a color television receiver to determine the ratio between the chrominance-subcarrier frequency and the horizontal frequency, which ratio is fixed at the transmitting end, both in the PAL system and the NTSC system.
摘要翻译：本发明提供一种数字电路，用于在所选择的测量周期期间发生两个信号F1和F2的预定频率比v = f1 / f2时产生二进制信号输出。该电路特别适用于彩色电视接收机，以确定在PAL系统和NTSC系统中的色度 - 副载波频率与水平频率之间的比率，该比率固定在发送端。

2. 发明授权

US4509072A Digital circuit for providing a binary signal on the occurrence of a predetermined frequency ratio of two signals 失效
标题翻译：数字电路，用于在出现两个信号的预定频率比时提供二进制信号
公开(公告)号：US4509072A
公开(公告)日：1985-04-02
申请号：US592900
申请日：1984-03-23
申请人： Herbert Elmis , Adrian Klar
发明人： Herbert Elmis , Adrian Klar
IPC分类号： H04N9/44
CPC分类号： H04N9/44
摘要： The invention provides a digital circuit for generating a binary signal output when a predetermined frequency ratio, v=f1/f2, of two signals F1 and F2 occurs during a selected measuring period. The circuit is particularly adapted for use in a color television receiver to determine the ratio between the chrominance-subcarrier frequency and the horizontal frequency, which ratio is fixed at the transmitting end, both in the PAL system and the NTSC system.
摘要翻译：本发明提供一种数字电路，用于在所选择的测量周期期间发生两个信号F1和F2的预定频率比v = f1 / f2时产生二进制信号输出。该电路特别适用于彩色电视接收机，以确定在PAL系统和NTSC系统中的色度 - 副载波频率与水平频率之间的比率，该比率固定在发送端。

3. 发明授权

US4710814A Television sound receiving circuit for at least one sound channel contained in an RF signal 失效
标题翻译：用于包含在RF信号中的至少一个声音通道的电视声音接收电路
公开(公告)号：US4710814A
公开(公告)日：1987-12-01
申请号：US899973
申请日：1986-08-25
申请人： Gerhard G. Gassmann , Hermannus Schat , Herbert Elmis , Bernd Novotny , Otmar Kappeler , Dietmar Ehrhardt
发明人： Gerhard G. Gassmann , Hermannus Schat , Herbert Elmis , Bernd Novotny , Otmar Kappeler , Dietmar Ehrhardt
IPC分类号： H04N5/60 , H04N7/04 , G06G7/14 , H03K5/00
CPC分类号： H04N5/607 , H04N5/60
摘要： A television sound receiving circuit for at least one sound channel contained in an RF signal converts the transmitted or already down-converted television signal as a composite signal to the baseband in a single-sideband demodulator circuit using the "phasing method", separates the first sound channel, corresponding to a lower sideband, and the second sound channel, corresponding to an upper sideband, and produces first and second sound signals at the desired frequency by subsequent frequency demodulation. Also shown are the interfaces for possible digitization and an advantageous use of the interfaces in which picture and sound signals are digitized together. The data can be combined into a single data stream which can be transferred over a bus system and is separable into the individual components if required.
摘要翻译：用于包含在RF信号中的至少一个声音通道的电视声音接收电路使用“定相方法”在单边带解调器电路中将传输或已经下变频的电视信号作为复合信号转换到基带，将第一对应于下边带的声音通道和对应于上边带的第二声道，并且通过后续频率解调产生所需频率的第一和第二声音信号。还示出了用于可能的数字化的接口和将图像和声音信号数字化在一起的接口的有利使用。数据可以组合成单个数据流，可以通过总线系统传输，并且如果需要，可以分离到各个组件中。

4. 发明授权

US4504799A Digital frequency/phase locked loop 失效
标题翻译：数字频率/锁相环
公开(公告)号：US4504799A
公开(公告)日：1985-03-12
申请号：US282344
申请日：1981-07-10
申请人： Herbert Elmis , Bernd Novotny
发明人： Herbert Elmis , Bernd Novotny
IPC分类号： H03L7/099 , H03L7/18 , H04N5/12 , H03L7/22
CPC分类号： H03L7/18 , H03L7/0992
摘要： A frequency/phase locked loop for providing signals which are frequency and phase locked to signals at a reference frequency from a reference oscillator which is determinative of the frequency stability includes a frequency-controlled generator of a lower frequency stability. The frequency controlled generator is responsive to control signals for switching between first and second frequencies which are substantially higher than the reference frequency. The second frequency is approximately one to ten percent higher than the first frequency. The frequency divider coupled to the frequency generator provides an output signal at the same frequency as the reference oscillator. A digital phase comparator compares the outputs of the frequency divider with the reference signals. A digital integrating stage coupled to the comparator provides the control signals such that during a first portion of a period of the reference signals the first frequency is selected and during a second portion of the period the second frequency is selected.
摘要翻译：用于提供频率和相位锁定信号的频率/锁相环路，其中频率和相位锁定来自参考频率的参考频率的信号，该参考振荡器确定频率稳定性，包括频率稳定性较低的频率控制发生器。频率控制发生器响应于用于在基本上高于参考频率的第一和第二频率之间切换的控制信号。第二频率比第一频率高大约百分之一到十。耦合到频率发生器的分频器提供与参考振荡器相同频率的输出信号。数字相位比较器将分频器的输出与参考信号进行比较。耦合到比较器的数字积分级提供控制信号，使得在参考信号的周期的第一部分期间选择第一频率，并且在周期的第二部分期间，选择第二频率。

5. 发明授权

US4489342A MOSFET Integrated delay circuit for digital signals and its use in color-televison receivers 失效
标题翻译： MOSFET用于数字信号的集成延迟电路及其在彩色电视接收机中的应用
公开(公告)号：US4489342A
公开(公告)日：1984-12-18
申请号：US349228
申请日：1982-02-16
申请人： Wolfgang Gollinger , Hermannus Schat , Dieter Holzmann , Herbert Elmis , Holger Struthoff , Detlev Kunz
发明人： Wolfgang Gollinger , Hermannus Schat , Dieter Holzmann , Herbert Elmis , Holger Struthoff , Detlev Kunz
IPC分类号： H03K5/04 , H03H11/26 , H03H17/00 , H03K3/03 , H03K3/354 , H03K5/00 , H03K5/13 , H04N5/93
CPC分类号： H03K5/133 , H03H11/265 , H03H17/0009 , H03K3/0315 , H03K3/354 , H03K2005/00071 , H03K2005/00195
摘要： To adjust time delays in equidistant steps, an inverter chain is provided with an even number of static inverters of identical topology. The output of one of the even-numbered inverters is connected to the signal output via a selector switch. During suitable frequency-measuring periods, an odd number of inverters is connected to form a ring by directly coupling the output of an odd-numbered inverter to the input of the first, and a digital measuring arrangement determines the time delay of the ring-connected portion from the frequency of the ring's self-excited oscillation. The output signal of the measuring arrangement is used to adjust the time delay of the inverter chain.
摘要翻译：为了在等距步调节时间延迟，逆变器链上设置了偶数个具有相同拓扑结构的静态逆变器。其中一个偶数反相器的输出通过选择开关连接到信号输出。在合适的频率测量周期中，通过将奇数反相器的输出直接耦合到第一个反相器的输入，奇数个反相器连接形成一个环，数字测量装置确定环形连接的时间延迟部分从环的自激振荡的频率。测量装置的输出信号用于调整变频器链的时间延迟。

6. 发明授权

US4506297A Integrated circuit for television receivers comprising a sonic separator with a clamping circuit 失效
标题翻译：用于电视接收机的集成电路包括具有钳位电路的声音分离器
公开(公告)号：US4506297A
公开(公告)日：1985-03-19
申请号：US391623
申请日：1982-06-24
申请人： Herbert Elmis
发明人： Herbert Elmis
IPC分类号： H04N5/08 , H04N5/12 , H04N5/18 , H04N5/10 , H04N7/00
CPC分类号： H04N5/126
摘要： To prevent the separation-level shift occurring in the clamping circuit during the transmitted vertical synchronizing pulses or during prolonged interference pulses, a pulse opening an electronic switch (S) inserted between the clamping circuit and one RC section thereof is generated by means of a coincidence stage (KO), a gate circuit (TS), an inverter (I), and an AND gate (U). The clamping circuit is thus unblocked only during the horizontal synchronizing pulses, so that no shift of the separation level can occur during the vertical synchronizing pulses or during any interference pulses in the composite color signal (F).
摘要翻译：为了防止在发送的垂直同步脉冲期间或在延长的干扰脉冲期间在钳位电路中发生分离电平偏移，打开插入在钳位电路和其一个RC部分之间的电子开关（S）的脉冲通过重合产生（KO），门电路（TS），逆变器（I）和与门（U）。因此钳位电路仅在水平同步脉冲期间被解除阻塞，使得在垂直同步脉冲期间或在复合颜色信号（F）中的任何干扰脉冲期间不会发生分离电平的偏移。

7. 发明授权

US4578705A Digital circuit for synchronizing a pulse train 失效
标题翻译：用于同步脉冲串的数字电路
公开(公告)号：US4578705A
公开(公告)日：1986-03-25
申请号：US592920
申请日：1984-03-23
申请人： Herbert Elmis , Reiner Backes
发明人： Herbert Elmis , Reiner Backes
IPC分类号： H04N5/12 , H04N5/04 , H03L7/00
CPC分类号： H04N5/12
摘要： A digital synchronization operation circuit synchronizes a pulse train with horizontal synchronizing pulses contained in a received standard television signal which, after being demodulated in the television receiver, is present as the composite color signal and which is fed to an analog-to-digital converter clocked by a clock signal. The digital synchronization separation circuit has an improved phase resolution such that the phase resolution is greater than the resolution provided by the pulse width of clocking signals.
摘要翻译：数字同步操作电路将脉冲串与包含在接收的标准电视信号中的水平同步脉冲同步，该标准电视信号在电视接收机中被解调后作为合成彩色信号存在，并被馈送到时钟频率为模数转换器通过时钟信号。数字同步分离电路具有改进的相位分辨率，使得相位分辨率大于由时钟信号的脉冲宽度提供的分辨率。

8. 发明授权

US4494243A Frequency divider presettable to fractional divisors 失效
$Frequency divider presettable to fractional divisors$
标题翻译：分频器可预设为分数除数
公开(公告)号：US4494243A
公开(公告)日：1985-01-15
申请号：US442055
申请日：1982-11-16
申请人： Herbert Elmis
发明人： Herbert Elmis
IPC分类号： H03K23/64 , G06F7/68 , H03K21/36
CPC分类号： H03K21/38 , G06F7/68 , H03K23/68
摘要： Division by fractions is accomplished with a counter (Z) presettable to integers and a digitally adjustable delay line (V) following this counter. The fractional parts (b) of the divisor, which are held in decimal point representation (a+0.b) in a divisor register (R), are applied to a first adder (A1) followed by a buffer memory (S), and the integral parts (a) of this divisor are applied to a second adder (A2). The output of the buffer memory (S) is coupled to the set input (Es) of the delay line (V) and to the second input (E2) of the first adder (A1). Thus, at the input of the delay line (V), the number corresponding to the fractional parts (b) is continuously increased by the fractional parts (b) until the overflow output (Ao) of the first adder (A1) provides a signal which is applied to the least significant digit (LB) of the first input (E1) of the second adder (A2). One unit is thus added to the integral parts (a), and the counter (Z) counts one additional digit for one cycle. For arbitrary fractional divisors, the maximum phase-jitter amplitude is equal to the smallest adjustable time delay and, hence, considerably smaller than the clock period (T') of the signal to be divided (F).
摘要翻译：按计数器（Z）预置为整数，并在该计数器之后的数字可调延迟线（V）完成分数。在除数寄存器（R）中以小数点表示（a + 0.b）保持的除数的分数部分（b）被施加到第一加法器（A1），随后是缓冲存储器（S）并且该除数的积分部分（a）被施加到第二加法器（A2）。缓冲存储器（S）的输出耦合到延迟线（V）的设定输入（Es）和第一加法器（A1）的第二输入端（E2）。因此，在延迟线（V）的输入端，对应于小数部分（b）的数字被连续增加了小数部分（b），直到第一加法器（A1）的溢出输出（Ao）提供信号其被应用于第二加法器（A2）的第一输入（E1）的最低有效位（LB）。因此，一个单元被添加到积分部件（a）中，并且计数器（Z）对一个周期计数一个附加数字。对于任意的小数除数，最大相位抖动幅度等于最小可调时间延迟，因此相当于要分割信号（F）的时钟周期（T'）。

9. 发明授权

US4471299A Circuit for digital phase difference measuring and synchronizing between pulse trains 失效
标题翻译：脉冲串数字相位差测量和同步电路
公开(公告)号：US4471299A
公开(公告)日：1984-09-11
申请号：US509979
申请日：1983-06-30
申请人： Herbert Elmis
发明人： Herbert Elmis
IPC分类号： G01R25/08 , G01S3/805 , H03L7/099 , H04N5/12 , G01R25/00
CPC分类号： G01R25/08 , G01S3/8055 , H03L7/0992 , H04N5/12
摘要： A circuit for digitally evaluating the magnitude of the phase error between a reference and a locally generated train (sequence) of pulses. The reference train (sequence) may be, for example, the received horizontal sync pulse in a television receiver and the locally generated synchronizable horizontal trigger of the receiver. The reference pulse train (sequence) contains statistical noise and noise pulses and by multiple phase error sampling (digital) and averaging a much more accurate phase error measurement is obtained. Circuits for directly synchronizing the local trigger generator from the measured phase error are also included.
摘要翻译：用于数字评估参考和本地产生的脉冲序列（序列）之间的相位误差的大小的电路。参考列（序列）可以是例如电视接收机中的接收到的水平同步脉冲和接收机的本地产生的可同步的水平触发。参考脉冲串（序列）包含统计噪声和噪声脉冲，并通过多相位误差采样（数字）和平均得到更准确的相位误差测量。还包括用于从测量的相位误差直接同步本地触发发生器的电路。

10. 发明授权

US5798802A Video signal clamping circuit 失效
标题翻译：视频信号钳位电路
公开(公告)号：US5798802A
公开(公告)日：1998-08-25
申请号：US791362
申请日：1997-01-30
申请人： Herbert Elmis , Heinrich Koehne , Herbert Alrutz , Hermann Zibold
发明人： Herbert Elmis , Heinrich Koehne , Herbert Alrutz , Hermann Zibold
IPC分类号： H04N5/16 , H04N5/18
CPC分类号： H04N5/18
摘要： A video signal clamping circuit for adapting the DC level of a composite video signal to the processing range of a digital video signal processing device, includes an isolating capacitor in the analog video signal path and a controlled current source which is connected to a floating isolating-capacitor terminal and charges or discharges the isolating capacitor solely by means of a positive or negative clamping current, with the value and sign of the clamping pulses being digitally controlled by a comparator circuit which compares predetermined reference values of the composite video signal with mode-dependent comparison values.
摘要翻译：一种视频信号钳位电路，用于将复合视频信号的DC电平适配到数字视频信号处理装置的处理范围，包括模拟视频信号路径中的隔离电容器和连接到浮动隔离电路的受控电流源，电容器端子，并且仅通过正或负钳位电流对隔离电容器进行充电或放电，钳位脉冲的值和符号由比较器电路数字控制，比较器电路将复合视频信号的预定参考值与模式相关比较值。

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