专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050046601A1 PCM-to-PWM converter 有权
标题翻译： PCM到PWM转换器
公开(公告)号：US20050046601A1
公开(公告)日：2005-03-03
申请号：US10892531
申请日：2004-07-14
申请人： Herbert Alrutz , Dieter Lucking , Matthias Vierthaler
发明人： Herbert Alrutz , Dieter Lucking , Matthias Vierthaler
IPC分类号： H03K7/08 , H03K7/10 , H03K11/00 , H03M5/08 , H03M7/30
CPC分类号： H03M1/0614 , H03M1/822 , H03M3/358 , H03M3/506 , H03M5/08
摘要： The invention relates to a method and a device for converting a digital, pulse-coded coded signal (PCM) to a pulse-width-modulated signal (PWM), wherein the digital signal PCM, f(t) is multiplied by at least one derivative (f′(t), f″(t), . . . , f(n) (t)) of the signal (f(t)). The invention also relates to a technique for converting a digital pulse-coded signal (PCM) to a pulse-width-modulated signal (PWM), wherein to obtain a sampling rate sufficient for the pulse-width-modulated signal an oversampling of the digital signal is implemented with a first oversampling factor before the conversion and an second oversampling factor after the conversion, such that the product of the oversampling factors before and after conversion of the digital signal to the pulse-width-modulated signal corresponds at least to the value of the required oversampling factor.
摘要翻译：本发明涉及一种用于将数字脉冲编码编码信号（PCM）转换成脉冲宽度调制信号（PWM）的方法和装置，其中数字信号PCM，f（t）被乘以至少一个（f（t））的导数（f'（t），f“（t），...，f（（n）>（t））。本发明还涉及一种用于将数字脉冲编码信号（PCM）转换为脉冲宽度调制信号（PWM）的技术，其中为了获得对脉冲宽度调制信号足够的采样率，数字信号在转换之前用第一过采样因子和转换之后的第二过采样因子来实现，使得数字信号转换为脉宽调制信号之前和之后的过采样因子的乘积至少等于值的所需过采样因子。

2. 发明授权

US5262858A Method of converting the clock rate of a digitized signal 失效
标题翻译：转换数字化信号的时钟速率的方法
公开(公告)号：US5262858A
公开(公告)日：1993-11-16
申请号：US796566
申请日：1991-11-21
申请人： William Butera , Herbert Alrutz
发明人： William Butera , Herbert Alrutz
IPC分类号： H04N7/01 , H03H17/00 , H03H17/02 , H04B1/66 , H04N7/24 , H04N7/26 , H04N7/13
CPC分类号： H04N7/24 , H04B1/667 , H04N19/63
摘要： One-dimensional or multi-dimensional digitized signals are transformed into one-dimensional or multi-dimensional output signals by clock-rate conversion of subband signals. To synthesize the output signal at least one continuous subset of primary subband signals is used. The subset includes the subband signal with the lowest frequency range. During reproduction of images which are horizontally and vertically scanned and digitized, absolute and relative format changes can be implemented by the clock-rate conversion.
摘要翻译：通过子带信号的时钟速率转换将一维或多维数字化信号转换为一维或多维输出信号。为了合成输出信号，使用主要子带信号的至少一个连续子集。该子集包括具有最低频率范围的子带信号。在水平和垂直扫描和数字化的图像的再现期间，可以通过时钟速率转换来实现绝对和相对格式的改变。

3. 发明申请

US20060069706A1 Random number generator and method for generating random numbers 有权
公开(公告)号：US20060069706A1
公开(公告)日：2006-03-30
申请号：US11238158
申请日：2005-09-28
申请人： Dejan Lazich , Herbert Alrutz , Miodrag Temerinac , Steffen Schober
发明人： Dejan Lazich , Herbert Alrutz , Miodrag Temerinac , Steffen Schober
IPC分类号： G06F7/58
CPC分类号： H04L9/0861 , G06F7/588 , H03K3/84
摘要： The invention relates to a method for generating random numbers in which oscillating digital output signals (A1, A2, . . . , AL) of unequal or equal periodicity are generated by at least two ring oscillators (32, 33, 34), an external parity signal (PS) representing a logical state (“0,” “1”) being generated when an odd number of the output signals (A1, A2, . . . , AL) take on a specified logical state (“1”). According to the invention, the external parity signal (PS) is fed back to an external parity input (36, 37, 38) of each of the respective ring oscillators (32, 33, 34). The invention further relates to a random number generator having at least two ring oscillators (32, 33, 34), made up in particular of independently free-running inverter chains with feedback having an odd number (K) of series-connected inverters (inv1,2, inv2,1, inv3,1, . . . , invi,j, . . . , invL,KL) that generate oscillating digital output signals (A1, A2, . . . , AL) of unequal or equal periodicity, and having first parity signal generating means (XOR) that generate an external parity signal (PS) representing a logical state (“0,” “1”) when an odd number of the output signals (A1, A2, . . . , AL) take on a specified logical state (“1”). According to the invention, there are feedback means (xor1, xor2, xor3, xor4, . . . , xorL) that feed back the external parity signal (PS) to an external parity input (36, 37, 38) of each of the respective ring oscillators (32, 33, 34). In this invention the cooperation of chaotic dynamics (feedback of the parity signal) and true randomness (jitter due to thermal noise) in digital circuits, a novel theoretical principle for generating random numbers, has been made into an efficient practical solution.

4. 发明授权

US6137349A Filter combination for sampling rate conversion 失效
标题翻译：滤波器组合用于采样率转换
公开(公告)号：US6137349A
公开(公告)日：2000-10-24
申请号：US110009
申请日：1998-07-02
申请人： Andreas Menkhoff , Herbert Alrutz
发明人： Andreas Menkhoff , Herbert Alrutz
IPC分类号： H03H17/00 , H03H17/02 , H03H17/06 , H03K5/00
CPC分类号： H03H17/0685 , H03H17/0621
摘要： A filter combination for sampling rate conversion is disclosed comprising a series combination of: an input low-pass filter (1) whose attenuation characteristic (tp1) has at least one first attenuation value (a1) in the vicinity of one-half and 1.5 times the frequency of a digitization clock (f1); a time-invariant interpolation filter (2) for increasing the number of samples from that of the first data sequence (d1) by an integral factor whose attenuation characteristic (tp2) has at least one second attenuation value (a2) in the vicinity of the frequency of the digitization clock (f1) and essentially at least one third attenuation value (a3) in the region between one-half and 1.5 times the frequency of the digitization clock; and a time-varying interpolation filter (3) for interpolating a data sequence (d5) provided at the output of the time-invariant interpolation filter (2), the attenuation characteristic (tp3) of the time-varying interpolation filter (3) having at least one fourth attenuation value (a4) in the vicinity of twice the frequency of the digitization clock (f1).
摘要翻译：公开了一种用于采样率转换的滤波器组合，其包括以下的串联组合：其衰减特性（tp1）具有至少一个第一衰减值（a1）在一半和1.5倍附近的输入低通滤波器（1）数字化时钟（f1）的频率; 用于将第一数据序列（d1）的样本数量增加到其衰减特性（tp2）在其附近的衰减特性（tp2）至少有一个第二衰减值（a2）的积分因子的时不变内插滤波器（2）数字化时钟（f1）的频率和基本上在数字化时钟的频率的一半和1.5倍之间的区域中的至少一个第三衰减值（a3）; 以及时变内插滤波器（3），用于内插设置在时间不变插值滤波器（2）的输出端的数据序列（d5），时变内插滤波器（3）的衰减特性（tp3）具有在数字化时钟（f1）的频率的两倍附近的至少四个衰减值（a4）。

5. 发明授权

US07406492B1 Digital filter combination for interpolation 失效
标题翻译：用于插值的数字滤波器组合
公开(公告)号：US07406492B1
公开(公告)日：2008-07-29
申请号：US08984735
申请日：1997-12-04
申请人： Andreas Menkhoff , Herbert Alrutz
发明人： Andreas Menkhoff , Herbert Alrutz
IPC分类号： G06F17/10
CPC分类号： G06F17/17
摘要： A digital filter combination for interpolating primary sample values of a sampled signal using an mth-order discrete-time filter and a kth-order continuous time interpolation filter, with m≧3 and k≧2, wherein the discrete-time filter forms n secondary sample values from at least m+1 primary sample values at equal time intervals, with n≧m, and the continuous-time interpolation filter forms from at least part of the n secondary sample values an interpolated value whose temporal position with respect to that of the primary sample values is predeterminable by a normalized interpolating instant dp=tin/T, where tin is the absolute interpolating instant, and T is the period of the primary sampling rate.
摘要翻译：一种数字滤波器组合，用于使用m阶= 3和k> = 2的第m级离散时间滤波器和第k级连续时间内插滤波器内插采样信号的初级采样值，其中离散时间滤波器形式 n个等于时间间隔的至少m + 1个初级样本值的二次样本值，其中n> = m，并且连续时间内插滤波器从n个次要样本值的至少一部分形成内插值，其相对于与原始样本值的值是可以通过 / T中的归一化内插时刻dp = t 来确定的，其中中的t>是绝对内插时刻，T是主要采样率。

6. 发明申请

US20120057695A1 CIRCUITS FOR MODULAR ARITHMETIC BASED ON THE COMPLEMENTATION OF CONTINUED FRACTIONS 审中-公开
标题翻译：基于继续分段补充的模块算术电路
公开(公告)号：US20120057695A1
公开(公告)日：2012-03-08
申请号：US12440340
申请日：2007-06-26
申请人： Dejan Lazich , Herbert Alrutz , Christian Senger
发明人： Dejan Lazich , Herbert Alrutz , Christian Senger
IPC分类号： H04L9/28
CPC分类号： G06F7/728 , G06F7/724
摘要： A method for calculating a modular multiplication of integers a and b or polynomials a(x) and b(x) for a modulus N. The method including (i) calculating a supplemental product continued fraction c=(ab+jN)/t by supplementing particular numerators of a product fraction (ab)/t represented as a continued fraction, and (ii) calculating a second supplemental product continued fraction r=(cd+kN)/t from a previously calculated modular remainder d=RN[t2] and the calculated supplemental product continued fraction c.
摘要翻译：用于计算模数N的整数a和b或多项式a（x）和b（x）的模乘相乘的方法。该方法包括（i）通过以下方法计算补充产品连续分数c =（ab + jN）/ t 补充表示为连续分数的产品分数（ab）/ t的特定分子，以及（ii）从先前计算的模块余数d = RN [t2]计算第二补充产品连续分数r =（cd + kN）/ t 和计算的补充产品持续分数c。

7. 发明授权

US07797361B2 System and method for generating random numbers using parity feedback 有权
标题翻译：使用奇偶校验反馈产生随机数的系统和方法
公开(公告)号：US07797361B2
公开(公告)日：2010-09-14
申请号：US11238158
申请日：2005-09-28
申请人： Dejan Lazich , Herbert Alrutz , Miodrag Temerinac , Steffen Schober
发明人： Dejan Lazich , Herbert Alrutz , Miodrag Temerinac , Steffen Schober
IPC分类号： G06F7/58 , H03B29/00
CPC分类号： H04L9/0861 , G06F7/588 , H03K3/84
摘要： A method for generating random numbers in which oscillating digital output signals of unequal or equal periodicity are generated by at least two ring oscillators, an external parity signal representing a logical state being generated when an odd number of the output signals take on a specified logical state, the external parity signal being fed back to an external parity input of each of the respective ring oscillators. Also, a random number generator having at least two ring oscillators made up of independently freewnning inverter chains with feedback having an odd number of series-connected inverters that generate oscillating digital output signals of unequal or equal periodicity, and having first panty signal generating mechanisms that generate an external parity signal representing a logical state when an odd number of the output signals take on a specified logical state.
摘要翻译：一种用于产生随机数的方法，其中由至少两个环形振荡器产生不等或相等周期的振荡数字输出信号，表示当奇数个输出信号具有指定逻辑状态时产生的逻辑状态的外部奇偶校验信号，外部奇偶校验信号被反馈到每个相应的环形振荡器的外部奇偶校验输入。另外，具有至少两个环形振荡器的随机数发生器，该环形振荡器由具有奇数个串联连接的反相器的反馈链独立地形成，产生具有不等周期或等周期的振荡数字输出信号，并且具有第一内裤信号产生机构，当奇数个输出信号采取指定的逻辑状态时，产生表示逻辑状态的外部奇偶校验信号。

8. 发明授权

US5798802A Video signal clamping circuit 失效
标题翻译：视频信号钳位电路
公开(公告)号：US5798802A
公开(公告)日：1998-08-25
申请号：US791362
申请日：1997-01-30
申请人： Herbert Elmis , Heinrich Koehne , Herbert Alrutz , Hermann Zibold
发明人： Herbert Elmis , Heinrich Koehne , Herbert Alrutz , Hermann Zibold
IPC分类号： H04N5/16 , H04N5/18
CPC分类号： H04N5/18
摘要： A video signal clamping circuit for adapting the DC level of a composite video signal to the processing range of a digital video signal processing device, includes an isolating capacitor in the analog video signal path and a controlled current source which is connected to a floating isolating-capacitor terminal and charges or discharges the isolating capacitor solely by means of a positive or negative clamping current, with the value and sign of the clamping pulses being digitally controlled by a comparator circuit which compares predetermined reference values of the composite video signal with mode-dependent comparison values.
摘要翻译：一种视频信号钳位电路，用于将复合视频信号的DC电平适配到数字视频信号处理装置的处理范围，包括模拟视频信号路径中的隔离电容器和连接到浮动隔离电路的受控电流源，电容器端子，并且仅通过正或负钳位电流对隔离电容器进行充电或放电，钳位脉冲的值和符号由比较器电路数字控制，比较器电路将复合视频信号的预定参考值与模式相关比较值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式