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1. 发明授权

US06369008B1 Cleaning solutions for removing contaminants from the surfaces of semiconductor substrates and cleaning methods using the same 失效
标题翻译：用于从半导体衬底的表面去除污染物的清洁溶液和使用其的清洁方法
公开(公告)号：US06369008B1
公开(公告)日：2002-04-09
申请号：US09665622
申请日：2000-09-19
申请人： Heon-jae Ha , Dae-hyuk Chung , In-seak Hwang , Yong-sun Ko
发明人： Heon-jae Ha , Dae-hyuk Chung , In-seak Hwang , Yong-sun Ko
IPC分类号： C11D710
CPC分类号： C11D3/3947 , C11D7/08 , C11D7/10 , C11D11/0047 , H01L21/02063 , H01L21/76814 , H01L21/76897
摘要： Cleaning solutions for removing contaminants from semiconductor substrates are provided and include from about 0.08 to about 0.1 percent by weight of hydrogen fluoride; from about 0.5 to about 0.6 percent by weight of ammonium fluoride; from about 24.9 to about 49.7 percent by weight of hydrogen peroxide; and from about 49.6 to about 74.5 percent by weight of water.
摘要翻译：提供了用于从半导体衬底去除污染物的清洁溶液，包括约0.08至约0.1重量％的氟化氢; 约0.5至约0.6重量％的氟化铵; 约24.9至约49.7重量％的过氧化氢; 和约49.6至约74.5重量％的水。

2. 发明授权

US06331478B1 Methods for manufacturing semiconductor devices having chamfered metal silicide layers 有权
标题翻译：具有倒角金属硅化物层的半导体器件的制造方法
公开(公告)号：US06331478B1
公开(公告)日：2001-12-18
申请号：US09685456
申请日：2000-10-09
申请人： Keum-joo Lee , In-seak Hwang , Yong-sun Ko , Chang-Iyoung Song
发明人： Keum-joo Lee , In-seak Hwang , Yong-sun Ko , Chang-Iyoung Song
IPC分类号： H01L214763
CPC分类号： H01L29/42376 , H01L21/28061 , H01L21/28114 , H01L21/32134 , H01L21/32139 , H01L21/76897 , H01L27/10873
摘要： Methods for manufacturing a semiconductor device, in which a chamfered metal silicide layer is formed by a 2-stage continuous wet etching process using different etchants, thereby resulting in a sufficient insulation margin between a lower conductive layer including the metal silicide layer and the contact plug self-aligned with the lower conductive layer are disclosed. In the manufacture of a semiconductor device, a mask pattern is formed on a metal silicide layer to expose a portion of the metal silicide layer. The exposed portion of the metal silicide layer is isotropically etched in a first etchant to form a metal silicide layer with a shallow groove, and defects due to the silicon remaining on the surface of the metal silicide layer with the shallow groove are removed using a second etchant, to form a metal silicide layer with a smooth surface. Microelectronic structures produced by methods of the present invention are also disclosed.
摘要翻译：制造半导体器件的方法，其中通过使用不同蚀刻剂的2阶段连续湿蚀刻工艺形成倒角金属硅化物层，从而在包括金属硅化物层的下导电层和接触插塞之间形成足够的绝缘边缘公开了与下导电层自对准。在半导体器件的制造中，在金属硅化物层上形成掩模图案以暴露金属硅化物层的一部分。金属硅化物层的暴露部分在第一蚀刻剂中被各向同性地蚀刻以形成具有浅槽的金属硅化物层，并且由于在具有浅槽的金属硅化物层的表面上残留的硅的缺陷被使用第二蚀刻剂，以形成具有光滑表面的金属硅化物层。还公开了通过本发明的方法生产的微电子结构。

3. 发明授权

US06717231B2 Trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
标题翻译：沟槽隔离区域在其中具有防止过蚀刻的凹陷抑制层
公开(公告)号：US06717231B2
公开(公告)日：2004-04-06
申请号：US10224017
申请日：2002-08-20
申请人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
发明人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
摘要翻译：形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。掩模层可以包括氮化硅。然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。接下来，在凹陷抑制层上形成应力消除层。该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。然后用沟槽隔离层填充沟槽。然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

4. 发明授权

US08662958B2 Chemical-mechanical polishing apparatus for manufacturing semiconductor devices 失效
标题翻译：用于制造半导体器件的化学机械抛光装置
公开(公告)号：US08662958B2
公开(公告)日：2014-03-04
申请号：US12985048
申请日：2011-01-05
申请人： Jong-sun Ahn , In-seak Hwang , Soo-young Tak , Shin Kim , One-moon Chang
发明人： Jong-sun Ahn , In-seak Hwang , Soo-young Tak , Shin Kim , One-moon Chang
IPC分类号： B24B49/00
CPC分类号： B24B37/10 , B24B49/12
摘要： A chemical-mechanical polishing (CMP) apparatus for manufacturing a semiconductor device. The apparatus includes: a spin chuck for supporting and rotating a semiconductor wafer; a polisher comprising a polishing pad for planarizing a surface of the semiconductor wafer, the polisher moving along the surface of the semiconductor wafer by a polishing arm; and a polisher supporting device for supporting the polisher and maintaining the polisher in a horizontal state, while polishing an edge part of the surface of the semiconductor wafer, in order to improve polishing uniformity of a center part and the edge part of the semiconductor wafer. Accordingly, polishing uniformity of the center part and edge part of the semiconductor wafer may be improved, and a height of the polisher supporting device may be optimized according to a polishing degree. Also, the polisher may be easily supported, wear and tear of the support head may be minimized, and the support head may function as a conditioner.
摘要翻译：一种用于制造半导体器件的化学机械抛光（CMP）装置。该装置包括：用于支撑和旋转半导体晶片的旋转卡盘; 抛光机，包括用于平坦化半导体晶片的表面的抛光垫，抛光机通过抛光臂沿着半导体晶片的表面移动; 以及用于在抛光半导体晶片的表面的边缘部分的同时在支撑抛光机并将抛光机保持在水平状态的抛光机支撑装置，以便改善半导体晶片的中心部分和边缘部分的抛光均匀性。因此，可以提高半导体晶片的中心部分和边缘部分的抛光均匀性，并且可以根据抛光度来优化抛光机支撑装置的高度。此外，可以容易地支撑抛光机，可以使支撑头的磨损和撕裂最小化，并且支撑头可用作调节器。

5. 发明申请

US20130052787A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130052787A1
公开(公告)日：2013-02-28
申请号：US13494328
申请日：2012-06-12
申请人： Kwang-wook Lee , Sang-jun Lee , In-seak Hwang , In-sang Jeon , Byoung-yong Gwak , Ho-kyun An
发明人： Kwang-wook Lee , Sang-jun Lee , In-seak Hwang , In-sang Jeon , Byoung-yong Gwak , Ho-kyun An
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L27/10852 , H01L21/76816 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91
摘要： A method of manufacturing a semiconductor device includes forming a bit line on a substrate comprising an active region; forming an interlayer insulating layer covering the bit line on the substrate; forming a first hole at a location of the active region through the interlayer insulating layer; forming a dummy contact layer by filling the first hole; forming a mold layer on the interlayer insulating layer and the dummy contact layer; forming a second hole at a location of the dummy contact layer through the mold layer; removing the dummy contact layer in the first hole through the second hole; forming an epitaxial layer on a portion of the active region, which is exposed at a lower surface of the first hole; and forming a lower electrode on internal surfaces of the first hole and the second hole.
摘要翻译：制造半导体器件的方法包括在包括有源区的衬底上形成位线; 形成覆盖所述基板上的所述位线的层间绝缘层; 在有源区的位置通过层间绝缘层形成第一孔; 通过填充第一孔形成虚拟接触层; 在层间绝缘层和虚拟接触层上形成模层; 在所述模拟接触层的位置处通过所述模制层形成第二孔; 通过第二孔去除第一孔中的虚拟接触层; 在所述有源区的在所述第一孔的下表面处露出的部分上形成外延层; 以及在所述第一孔和所述第二孔的内表面上形成下电极。

6. 发明申请

US20100093165A1 Method of fabricating integrated circuit semiconductor device having gate metal silicide layer 审中-公开
标题翻译：制造具有栅极金属硅化物层的集成电路半导体器件的方法
公开(公告)号：US20100093165A1
公开(公告)日：2010-04-15
申请号：US12453866
申请日：2009-05-26
申请人： Ki-ho Bae , Kwang-bok Kim , Choong-kee Seong , In-seak Hwang , Ki-jong Park , Kyung-hyun Kim
发明人： Ki-ho Bae , Kwang-bok Kim , Choong-kee Seong , In-seak Hwang , Ki-jong Park , Kyung-hyun Kim
IPC分类号： H01L21/8234 , H01L21/306
CPC分类号： H01L27/11519 , H01L21/0334 , H01L27/11521
摘要： Provided is a method of fabricating an integrated circuit semiconductor device. The method may include forming a plurality of gate patterns spaced apart from each other on a semiconductor substrate, the plurality of gate patterns including gate electrodes and gate capping patterns. After an interlayer insulating layer is formed to insulate the gate patterns, the interlayer insulating layer and the gate capping patterns may be planarized by etching until top surfaces of the gate electrodes are exposed. Gate metal silicide layers may be selectively formed on the gate electrodes.
摘要翻译：提供一种制造集成电路半导体器件的方法。所述方法可以包括在半导体衬底上形成彼此间隔开的多个栅极图案，所述多个栅极图案包括栅电极和栅极封盖图案。在形成层间绝缘层以使栅极图案绝缘之后，可以通过蚀刻来平坦化层间绝缘层和栅极封盖图案，直到栅电极的顶表面露出。可以在栅电极上选择性地形成栅极金属硅化物层。

7. 发明授权

US6146994A Method for forming self-aligned selective silicide layer using chemical mechanical polishing in merged DRAM logic 有权
标题翻译：在合并DRAM逻辑中使用化学机械抛光形成自对准选择性硅化物层的方法
公开(公告)号：US6146994A
公开(公告)日：2000-11-14
申请号：US298904
申请日：1999-04-26
申请人： In-seak Hwang
发明人： In-seak Hwang
IPC分类号： H01L21/31 , H01L21/8242 , H01L27/108 , H01L21/4763
CPC分类号： H01L27/10873 , H01L27/10894 , H01L27/10814 , H01L27/10891
摘要： A semiconductor device including a first area where a silicide layer is formed only on a gate electrode, and a second area where a silicide layer is formed both on the gate electrode and on source and drain areas is produced by a method wherein a polishing stopper and an oxide layer are sequentially stacked, the gate electrode is exposed in a self-aligned manner, and then a first silicide layer is formed to thereby suppress misalignment in the process of manufacturing a semiconductor device having a fine linear width. In the first area, when first and second insulating layers are stacked and contact holes are formed directly connected to the semiconductor substrate, a second silicide layer is formed at the bottoms of the contact holes, to reduce contact resistance and leakage current.
摘要翻译：一种半导体器件，其包括仅在栅电极上形成硅化物层的第一区域，以及在栅极电极和源极和漏极区域上形成硅化物层的第二区域，其中抛光步骤和依次层叠氧化物层，以自对准的方式露出栅电极，然后形成第一硅化物层，从而抑制制造具有微细线宽度的半导体器件的工艺中的未对准。在第一区域中，当堆叠第一和第二绝缘层并且直接连接到半导体衬底的接触孔时，在接触孔的底部形成第二硅化物层，以降低接触电阻和漏电流。

8. 发明授权

US08748254B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08748254B2
公开(公告)日：2014-06-10
申请号：US13494328
申请日：2012-06-12
申请人： Kwang-wook Lee , Sang-jun Lee , In-seak Hwang , In-sang Jeon , Byoung-yong Gwak , Ho-kyun An
发明人： Kwang-wook Lee , Sang-jun Lee , In-seak Hwang , In-sang Jeon , Byoung-yong Gwak , Ho-kyun An
IPC分类号： H01L21/00
CPC分类号： H01L27/10852 , H01L21/76816 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91
摘要： A method of manufacturing a semiconductor device includes forming a bit line on a substrate comprising an active region; forming an interlayer insulating layer covering the bit line on the substrate; forming a first hole at a location of the active region through the interlayer insulating layer; forming a dummy contact layer by filling the first hole; forming a mold layer on the interlayer insulating layer and the dummy contact layer; forming a second hole at a location of the dummy contact layer through the mold layer; removing the dummy contact layer in the first hole through the second hole; forming an epitaxial layer on a portion of the active region, which is exposed at a lower surface of the first hole; and forming a lower electrode on internal surfaces of the first hole and the second hole.
摘要翻译：制造半导体器件的方法包括在包括有源区的衬底上形成位线; 形成覆盖所述基板上的所述位线的层间绝缘层; 在有源区的位置通过层间绝缘层形成第一孔; 通过填充第一孔形成虚拟接触层; 在层间绝缘层和虚拟接触层上形成模层; 在所述模拟接触层的位置处通过所述模制层形成第二孔; 通过第二孔去除第一孔中的虚拟接触层; 在所述有源区的在所述第一孔的下表面处露出的部分上形成外延层; 以及在所述第一孔和所述第二孔的内表面上形成下电极。

9. 发明申请

US20110171882A1 CHEMICAL-MECHANICAL POLISHING APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICES 失效
标题翻译：用于制造半导体器件的化学机械抛光装置
公开(公告)号：US20110171882A1
公开(公告)日：2011-07-14
申请号：US12985048
申请日：2011-01-05
申请人： Jong-sun Ahn , In-seak Hwang , Soo-young Tak , Shin Kim , One-moon Chang
发明人： Jong-sun Ahn , In-seak Hwang , Soo-young Tak , Shin Kim , One-moon Chang
IPC分类号： B24B41/06 , B24B49/00
CPC分类号： B24B37/10 , B24B49/12
摘要： A chemical-mechanical polishing (CMP) apparatus for manufacturing a semiconductor device. The apparatus includes: a spin chuck for supporting and rotating a semiconductor wafer; a polisher comprising a polishing pad for planarizing a surface of the semiconductor wafer, the polisher moving along the surface of the semiconductor wafer by a polishing arm; and a polisher supporting device for supporting the polisher and maintaining the polisher in a horizontal state, while polishing an edge part of the surface of the semiconductor wafer, in order to improve polishing uniformity of a center part and the edge part of the semiconductor wafer. Accordingly, polishing uniformity of the center part and edge part of the semiconductor wafer may be improved, and a height of the polisher supporting device may be optimized according to a polishing degree. Also, the polisher may be easily supported, wear and tear of the support head may be minimized, and the support head may function as a conditioner.
摘要翻译：一种用于制造半导体器件的化学机械抛光（CMP）装置。该装置包括：用于支撑和旋转半导体晶片的旋转卡盘; 抛光机，包括用于平坦化半导体晶片的表面的抛光垫，抛光机通过抛光臂沿着半导体晶片的表面移动; 以及用于在抛光半导体晶片的表面的边缘部分的同时在支撑抛光机并将抛光机保持在水平状态的抛光机支撑装置，以便改善半导体晶片的中心部分和边缘部分的抛光均匀性。因此，可以提高半导体晶片的中心部分和边缘部分的抛光均匀性，并且可以根据抛光度来优化抛光机支撑装置的高度。此外，可以容易地支撑抛光机，可以使支撑头的磨损和撕裂最小化，并且支撑头可用作调节器。

10. 发明授权

US06461937B1 Methods of forming trench isolation regions having recess-inhibiting layers therein that protect against overetching 失效
标题翻译：形成其中具有防止过蚀刻的凹陷抑制层的沟槽隔离区的方法
公开(公告)号：US06461937B1
公开(公告)日：2002-10-08
申请号：US09479442
申请日：2000-01-07
申请人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
发明人： Sung-eui Kim , Keum-joo Lee , In-seak Hwang , Young-sun Koh , Dong-ho Ahn , Moon-han Park , Tai-su Park
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a semiconductor substrate having a trench therein and a masking layer thereon extending adjacent the trench. The masking layer may comprise silicon nitride. A recess-inhibiting layer is then formed on a sidewall of the trench and on a sidewall of the masking layer. Next, a stress-relief layer is formed on the recess-inhibiting layer. This stress-relief layer extends opposite the sidewall of the trench and opposite the sidewall of the masking layer and may comprise silicon nitride. The trench is then filled with a trench isolation layer. A sequence of planarization or etch-back steps are then performed to remove the masking layer and also align an upper surface of the trench isolation layer with a surface of the substrate. At least a portion of the masking layer is removed using a first etchant (e.g., phosphoric acid) that selectively etches the masking layer and the stress-relief layer at faster rates than the first recess-inhibiting layer. The recess-inhibiting layer is formed directly on a sidewall of the masking layer in order to limit the extent to which the outer surfaces of the stress-relief layer are exposed to the first etchant. In this manner, recession of the stress-relief layer and the voids that may subsequently develop as a result of the recession can be reduced. Multiple thin stress-relief layers may also be provided and these multiple layers provide a degree of stress-relief that is comparable with a single much thicker stress-relief layer.
摘要翻译：形成沟槽隔离区域的方法包括以下步骤：在其中形成具有沟槽的半导体衬底和其上邻近沟槽延伸的掩模层。掩模层可以包括氮化硅。然后在沟槽的侧壁和掩模层的侧壁上形成凹陷抑制层。接下来，在凹陷抑制层上形成应力消除层。该应力消除层与沟槽的侧壁相对并且与掩模层的侧壁相对延伸并且可以包括氮化硅。然后用沟槽隔离层填充沟槽。然后执行一系列平面化或蚀刻步骤以去除掩模层，并且还使沟槽隔离层的上表面与衬底的表面对准。使用第一蚀刻剂（例如磷酸）去除掩模层的至少一部分，其以比第一凹陷抑制层更快的速率选择性地蚀刻掩模层和应力消除层。凹陷抑制层直接形成在掩模层的侧壁上，以限制应力消除层的外表面暴露于第一蚀刻剂的程度。以这种方式，可以减少应力消除层的凹陷和随后可能由于凹陷而形成的空隙。还可以提供多个薄的应力消除层，并且这些多层提供与单个更厚的应力消除层相当的应力消除程度。

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