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1. 发明授权

US4619039A Method of manufacturing a semiconductor device and device manufactured by the use of the method 失效
标题翻译：通过使用该方法制造半导体器件和器件的方法
公开(公告)号：US4619039A
公开(公告)日：1986-10-28
申请号：US657644
申请日：1984-10-04
申请人： Henricus G. R. Maas , Jan W. Slotboom , Johannes A. Appels , Kazimierz Osinski
发明人： Henricus G. R. Maas , Jan W. Slotboom , Johannes A. Appels , Kazimierz Osinski
IPC分类号： H01L29/762 , H01L21/339 , H01L29/417 , H01L29/423 , H01L29/76 , H01L29/772 , H01L21/90
CPC分类号： H01L29/66954 , H01L29/42396 , Y10S438/911
摘要： A method of manufacturing a semiconductor device having narrow, coplanar, silicon electrodes which are separated from each other by grooves or slots having a width in the submicron range. The electrodes are alternatively covered by an oxide and by an oxidation-preventing layer, such as silicon nitride. According to the invention, a first and second electrode which are both covered with one of these layers, and which enclose a third electrode covered by the other of these layers, are first interconnected inside a connection region. Two of the three electrodes are separated from the connection region by etching. By selective etching, overlapping contact windows are provided on all three electrodes, and inside the contact windows etching of the groove is omitted.
摘要翻译：一种制造半导体器件的方法，该半导体器件具有窄的，共面的硅电极，它们通过宽度在亚微米范围内的槽或狭缝彼此分开。电极交替地由氧化物和诸如氮化硅的防氧化层覆盖。根据本发明，第一和第二电极都被这些层中的一个覆盖，并且包围由这些层中的另一个覆盖的第三电极首先在连接区域内互连。三个电极中的两个通过蚀刻与连接区域分离。通过选择性蚀刻，在所有三个电极上设置重叠的接触窗口，并且在接触窗口的内部省略了凹槽的蚀刻。

2. 发明授权

US4574468A Method of manufacturing a semiconductor device having narrow coplanar silicon electrodes 失效
标题翻译：制造具有窄共面硅电极的半导体器件的方法
公开(公告)号：US4574468A
公开(公告)日：1986-03-11
申请号：US657631
申请日：1984-10-04
申请人： Jan W. Slotboom , Henricus G. R. Maas , Johannes A. Appels , Francois M. Klaassen
发明人： Jan W. Slotboom , Henricus G. R. Maas , Johannes A. Appels , Francois M. Klaassen
IPC分类号： H01L29/762 , H01L21/033 , H01L21/339 , H01L27/10 , H01L29/76 , H01L29/772 , H01L21/90
CPC分类号： H01L29/66954 , H01L21/033
摘要： A method of manufacturing a semiconductor device, for example an SPS memory having narrow coplanar silicon electrodes. The electrodes are formed by etching grooves or slots (10) having a width in the submicron range into a polycrystalline silicon layer (3), the slot width being defined by the oxidized edge (6) of a silicon auxiliary layer (5). The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. According to the invention, the electrodes formed covered by silicon oxide (3B, 13B) are first interconnected pairwise, whereupon they are separated from each other in a separate etching step and are provided with self-aligned contact windows (15). Thus, the very narrow electrodes can be contacted without technological problems and memory cells of very small dimensions can be obtained.
摘要翻译：一种制造半导体器件的方法，例如具有窄共面硅电极的SPS存储器。通过将具有亚微米范围宽度的槽或槽（10）蚀刻成多晶硅层（3）形成电极，槽宽度由硅辅助层（5）的氧化边缘（6）限定。电极被氧化硅交替地覆盖，并且由包含氮化硅的层交替地覆盖。根据本发明，由氧化硅（3B，13B）覆盖的电极首先成对互连，于是它们在单独的蚀刻步骤中彼此分离并且设置有自对准的接触窗口（15）。因此，非常窄的电极可以在没有技术问题的情况下接触，并且可以获得非常小的尺寸的存储单元。

3. 发明授权

US4636826A Charge coupled devices having narrow coplanar silicon electrodes 失效
标题翻译：具有窄共面硅电极的电荷耦合器件
公开(公告)号：US4636826A
公开(公告)日：1987-01-13
申请号：US802499
申请日：1985-11-27
申请人： Jan W. Slotboom , Henricus G. R. Maas , Johannes A. Appels , Francois M. Klaassen
发明人： Jan W. Slotboom , Henricus G. R. Maas , Johannes A. Appels , Francois M. Klaassen
IPC分类号： H01L29/762 , H01L21/033 , H01L21/339 , H01L27/10 , H01L29/76 , H01L29/772 , H01L29/78 , H01L29/04
CPC分类号： H01L29/66954 , H01L21/033
摘要： In a semiconductor device, for example a SPS memory having narrow coplanar silicon electrodes, the electrodes are formed by etching grooves or slots having a width in the submicron range into a polycrystalline silicon layer with the slot width being defined by the oxidized edge of a silicon auxiliary layer. The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. The covered electrodes are first interconnected pairwise, whereupon they are separated from each other, and are provided with self-aligned contact windows. Thus, the very narrow electrodes can be contracted without technological problems and memory cells of very small dimensions are provided.

4. 发明授权

US4717689A Method of forming semimicron grooves in semiconductor material 失效
标题翻译：在半导体材料中形成半圆形槽的方法
公开(公告)号：US4717689A
公开(公告)日：1988-01-05
申请号：US776330
申请日：1985-09-16
申请人： Henricus G. R. Maas , Johannes A. Appels
发明人： Henricus G. R. Maas , Johannes A. Appels
IPC分类号： H01L21/302 , H01L21/033 , H01L21/3065 , H01L21/762 , H01L21/76
CPC分类号： H01L21/033 , H01L21/762 , Y10S438/947
摘要： On a layer having a stepped relief, such as a masking layer (4) having openings (5) on a substrate region, (2) a first layer (6) is provided, which, while maintaining the stepped relief, is covered by a second masking layer (8) and a convertible layer (9). By conversion of the convertible layer (9) (by means of ion implantation, oxidation, silicidation) this layer becomes selectively etchable. After removal of the non-converted parts, an intermediate mask (8) is formed with an opening in the second masking layer (8) along the edge of a depression (7). By means of the mask (8) thus obtained, grooves (11) are formed by anisotropic etching in the first layer (6) and in the subjacent substrate region (2) if required. When grooves are formed in a substrate region (2) of semiconductor material, these grooves may be filled with oxide (25) for forming insulated regions. If a first layer (6) of polycrystalline silicon is used on a substrate region (2) of silicon, this layer (6) can serve as a doping source and a connection, respectively. Thus, various kinds of transistors (MOSFET and bipolar transistors) can be manufactured. The second masking layer (8) and the convertible layer (9) may be realized, if required, as a single layer (65).
摘要翻译：在具有阶梯式浮雕的层上，例如在基板区域上具有开口（5）的掩模层（4），（2）第一层（6），其在保持阶梯式浮雕的同时被第二掩模层（8）和可转换层（9）。通过可转换层（9）（通过离子注入，氧化，硅化）的转化，该层变得可选择性地蚀刻。在去除未转换部件之后，沿着凹部（7）的边缘，在第二掩模层（8）中形成具有开口的中间掩模（8）。通过如此获得的掩模（8），如果需要，在第一层（6）和下层衬底区域（2）中通过各向异性蚀刻形成凹槽（11）。当在半导体材料的衬底区域（2）中形成沟槽时，这些沟槽可以填充用于形成绝缘区域的氧化物（25）。如果在硅的衬底区域（2）上使用多晶硅的第一层（6），则该层（6）可以分别用作掺杂源和连接。因此，可以制造各种晶体管（MOSFET和双极晶体管）。如果需要，可以将第二掩蔽层（8）和可转换层（9）实现为单层（65）。

5. 发明授权

US5008209A Method of manufacturing a semiconductor device including outdiffusion from polysilicon rims 失效
标题翻译：制造半导体器件的方法，其包括从多晶硅边缘扩散
公开(公告)号：US5008209A
公开(公告)日：1991-04-16
申请号：US463183
申请日：1990-01-10
申请人： Johannes A. Appels , Henricus G. R. Maas
发明人： Johannes A. Appels , Henricus G. R. Maas
IPC分类号： H01L21/8222 , H01L21/331 , H01L21/768 , H01L23/522 , H01L23/532 , H01L27/06 , H01L29/73 , H01L29/78
CPC分类号： H01L21/76838 , H01L23/522 , H01L23/53271 , H01L2924/0002 , Y10S148/131
摘要： A method of manufacturing a semiconductor device is set forth using anisotropic etching techniques, such as plasma etching and reactive ion etching to obtain interconnection patterns having accurately defined rims. Various different kinds of transistors can be manufacturing in the same semiconductor body using these techniques.
摘要翻译：使用诸如等离子体蚀刻和反应离子蚀刻之类的各向异性蚀刻技术来提供制造半导体器件的方法，以获得具有精确定义的边缘的互连图案。可以使用这些技术在相同的半导体主体中制造各种不同种类的晶体管。

6. 发明授权

US4750971A Method of manufacturing a semiconductor device 失效
公开(公告)号：US4750971A
公开(公告)日：1988-06-14
申请号：US7152
申请日：1987-01-27
申请人： Henricus G. R. Maas , Johannes A. Appels
发明人： Henricus G. R. Maas , Johannes A. Appels
IPC分类号： H01L29/762 , H01L21/033 , H01L21/308 , H01L21/321 , H01L21/331 , H01L21/339 , H01L29/73 , H01L29/732 , H01L29/76 , H01L29/772 , H01L21/306
CPC分类号： H01L29/66954 , H01L21/033 , H01L21/308 , H01L21/321 , Y10S438/911 , Y10S438/981
摘要： An improved method of manufacturing a semiconductor device having a narrow groove or slot is provided. There are formed on a substrate a heavily n-doped first silicon layer, and oxidation-preventing layer such as silicon nitride, and a weakly doped or undoped second silicon layer. By means of a single masking step, a part of the second silicon layer is removed to exposed portions of the oxidation preventing layer, and the remaining part is partially oxidized. A particle bombardment of the exposed portions of the oxidation-preventing layer is carried out with the oxidized part of the second silicon layer being a mask. Subsequently, the oxide on the second silicon layer is removed leaving non-exposed portions of the oxidation-preventing layer, and then the exposed portions of the oxidation-preventing layer on the first silicon layer are completely etched away. By thermal oxidation, a thin oxide layer is formed on the second silicon layer and an about ten times thicker oxide layer is formed on the first silicon layer. After the non-exposed portion of the oxidation-preventing layer has been etched away, the thin oxide layer on the second silicon layer is etched away entirely and the thicker oxide on the first silicon layer is etched away only superficially. After this, a groove is etched into the first silicon layer at the removed non-exposed portions of the oxidation-preventing layer while simultaneously removing the remaining parts of the second silicon layer.

7. 发明授权

US4659428A Method of manufacturing a semiconductor device and semiconductor device manufactured by means of the method 失效
标题翻译：通过该方法制造的半导体器件和半导体器件的制造方法
公开(公告)号：US4659428A
公开(公告)日：1987-04-21
申请号：US840164
申请日：1986-03-17
申请人： Henricus G. R. Maas , Johannes A. Appels
发明人： Henricus G. R. Maas , Johannes A. Appels
IPC分类号： H01L29/762 , H01L21/033 , H01L21/308 , H01L21/321 , H01L21/331 , H01L21/339 , H01L29/73 , H01L29/732 , H01L29/76 , H01L29/772 , H01L21/306
CPC分类号： H01L29/66954 , H01L21/033 , H01L21/308 , H01L21/321 , Y10S438/911 , Y10S438/981
摘要： An improved method of manufacturing a semiconductor device having a narrow groove or slot is provided. There are formed on a substrate a heavily n-doped first silicon layer, an oxidation-preventing layer such as silicon nitride, and a weakly doped or undoped second silicon layer. By means of a single masking step, a part of the second silicon layer is removed, and the remaining part is partially oxidized. The exposed portion of the oxidation-preventing layer is removed without a further masking step by using the oxidized remaining parts of the second silicon layer. Subsequently, the oxide on the second silicon layer is removed. By thermal oxidation, a thin oxide layer is formed on the second silicon layer and an about ten times thicker oxide layer is formed on the first silicon layer. After the exposed oxidation-preventing layer has been etched away, the oxide on the second silicon layer is etched away entirely, and the oxide on the first silicon layer is etched away only superficially. After this, a groove is etched at the removed portions of the exposed oxidation-preventing layer while simultaneously removing the remaining parts of the second silicon layer.
摘要翻译：提供了一种制造具有窄槽或槽的半导体器件的改进方法。在衬底上形成了大量n掺杂的第一硅层，诸如氮化硅的防氧化层，以及弱掺杂或未掺杂的第二硅层。通过单个掩蔽步骤，去除第二硅层的一部分，并且剩余部分被部分氧化。通过使用第二硅层的氧化剩余部分，不再进一步掩蔽步骤去除防氧化层的暴露部分。随后，去除第二硅层上的氧化物。通过热氧化，在第二硅层上形成薄的氧化物层，并且在第一硅层上形成约十倍厚的氧化物层。在暴露的氧化防止层被蚀刻掉之后，第二硅层上的氧化物被完全蚀刻掉，并且仅在表面上蚀刻第一硅层上的氧化物。之后，在暴露的氧化防止层的去除部分处蚀刻凹槽，同时去除第二硅层的剩余部分。

8. 发明授权

US4545110A Method of manufacturing an insulated gate field effect device 失效
标题翻译：绝缘栅场效应器件的制造方法
公开(公告)号：US4545110A
公开(公告)日：1985-10-08
申请号：US648603
申请日：1984-09-07
申请人： Henricus G. R. Maas , Francois M. Klaassen , Johannes A. Appels
发明人： Henricus G. R. Maas , Francois M. Klaassen , Johannes A. Appels
IPC分类号： H01L21/033 , H01L21/336 , H01L29/08 , H01L29/423 , H01L29/78 , H01L21/263
CPC分类号： H01L29/7834 , H01L21/0337 , H01L29/0847 , H01L29/6659 , H01L29/78
摘要： A method of manufacturing a field effect device is set forth where the source and drain zones have extensions of an accurately and reproducibly determined length adjoining the gate electrode. According to the present invention, an oxygen-preventing insulating layer is formed on a first silicon layer forming the gate electrode, and a second silicon layer is provided on the oxygen-preventing layer. A part of the second silicon layer is removed and the edges substantially coincide with the edges of the gate electrode to be formed. The edges of the remaining part of the second silicon layer are oxidized. Through successive maskless selective etching steps, the first silicon layer is exposed and etched away at the area of the oxidized etched portions. The extensions of the source and drain zones are implanted through the openings thus obtained.
摘要翻译：阐述了制造场效应器件的方法，其中源区和漏区具有与栅电极相邻的精确且可重复确定的长度的延伸。根据本发明，在形成栅电极的第一硅层上形成防氧绝缘层，在防氧化层上设置第二硅层。去除第二硅层的一部分，并且边缘与要形成的栅电极的边缘基本重合。第二硅层的剩余部分的边缘被氧化。通过连续的无掩模选择蚀刻步骤，第一硅层在氧化的蚀刻部分的区域被暴露并蚀刻掉。源极和漏极区域的延伸部分通过如此获得的开口植入。

9. 发明授权

US4449287A Method of providing a narrow groove or slot in a substrate region, in particular a semiconductor substrate region 失效
标题翻译：在衬底区域，特别是半导体衬底区域中提供窄槽或槽的方法
公开(公告)号：US4449287A
公开(公告)日：1984-05-22
申请号：US447844
申请日：1982-12-08
申请人： Henricus G. R. Maas , Johannes A. Appels
发明人： Henricus G. R. Maas , Johannes A. Appels
IPC分类号： H01L21/306 , G03F7/11 , H01G4/10 , H01G13/00 , H01L21/033 , H01L21/302 , H01L21/3065 , H01L21/308 , H01L21/331 , H01L21/336 , H01L21/339 , H01L21/76 , H01L29/73 , H01L29/76 , H01L29/772 , H01L29/78
CPC分类号： H01L29/66954 , G03F7/11 , H01G13/00 , H01L21/033 , H01L21/308 , Y10S438/911 , Y10S438/947
摘要： According to the invention, at least one oxidation-preventing layer (2) is provided on the substrate region (1), while on this layer there is provided an oxidizable layer (3). The oxidizable layer (3) is removed above part of the substrate region (1). An edge portion (5) of the oxidizable layer (3) is oxidized. Subsequently, at least the uncovered part of the oxidation-preventing layer (2) is removed selectively and the exposed part of the substrate region is thermally oxidized through part of its thickness, while practically only at the area of the oxidized edge portion (5) the substrate region (1) is exposed and is etched away through at least part of its thickness in order to form a groove (8), the oxidizable layer (3) and the oxidized edge portion (5) being removed completely. The substrate region may be a mono- or polycrystalline silicon layer. The oxidizable layer may consist of for instance polycrystalline silicon and may be coated with a second oxidation-preventing layer (4). If the substrate region is a masking layer, the slots provided therein may be used for doping purposes, for example, for forming channel stoppers, etc.Application in particular for the manufacture of integrated circuits and of gate electrodes spaced apart by very small distances in IGFET and CCD structures.FIG. 9 is suitable for abridgment.
摘要翻译：根据本发明，在基板区域（1）上设置至少一个氧化防止层（2），而在该层上设置有可氧化层（3）。可氧化层（3）在衬底区域（1）的一部分上方被去除。可氧化层（3）的边缘部分（5）被氧化。随后，选择性地去除防氧化层（2）的至少未覆盖部分，并且基板区域的暴露部分被部分厚度热氧化，实际上仅在氧化边缘部分（5）的区域处，衬底区域（1）被暴露并且通过其厚度的至少一部分被蚀刻掉以形成凹槽（8），可氧化层（3）和氧化边缘部分（5）被完全去除。衬底区域可以是单晶硅或多晶硅层。可氧化层可以由例如多晶硅组成，并且可以用第二防氧化层（4）涂覆。如果衬底区域是掩模层，则其中提供的槽可以用于掺杂目的，例如用于形成通道阻挡器等。特别地用于制造集成电路和以非常小的距离隔开的栅电极的制造 IGFET和CCD结构。图。 9适合于缓解。

10. 发明授权

US4689872A Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4689872A
公开(公告)日：1987-09-01
申请号：US771930
申请日：1985-09-03
申请人： Johannes A. Appels , Henricus G. R. Maas
发明人： Johannes A. Appels , Henricus G. R. Maas
IPC分类号： H01L29/78 , H01L21/033 , H01L21/225 , H01L21/331 , H01L21/336 , H01L23/532 , H01L29/73 , H01L29/732 , H01L21/22 , H01L21/265 , H01L21/318
CPC分类号： H01L29/66272 , H01L21/0337 , H01L21/2257 , H01L23/53271 , H01L2924/0002 , Y10S148/011 , Y10S148/051 , Y10S148/103 , Y10S438/911
摘要： For providing semiconductor zones (16, 18, 26) and contact metallization (19, 27) within an opening (9) in a self-registered manner, which opening is provided along its edge with polycrystalline connection parts (10) separated by an insulating material (15) from the metallization (19, 27), a protective layer (11) is formed which is maintained within the opening (9)until within this opening (9) the connection parts (10) are formed by anisotropic etching from a uniform layer of polycrystalline semiconductor material (10). The method is suitable for the manufacture of both bipolar transistors and field effect transistors.
摘要翻译：为了以自我注册的方式在开口（9）内提供半导体区域（16,18,26）和接触金属化（19,27），所述开口沿着其边缘设置有由绝缘体分隔的多晶连接部分（10）从金属化（19,27）的材料（15）形成保护层（11），其保持在开口（9）内，直到在该开口（9）内，连接部分（10）通过各向异性蚀刻从均匀的多晶半导体材料层（10）。该方法适用于制造双极晶体管和场效应晶体管。

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