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1. 发明授权

US06172408B2 Radiation-sensitive semiconductor device and method of manufacturing same 失效
标题翻译：辐射敏感半导体器件及其制造方法
公开(公告)号：US06172408B2
公开(公告)日：2001-01-09
申请号：US09273282
申请日：1999-03-19
申请人： Myron W. L. Seto , Stienke De Jager , Henricus G. R. Maas
发明人： Myron W. L. Seto , Stienke De Jager , Henricus G. R. Maas
IPC分类号： H01L31075
CPC分类号： H01L31/1892 , H01L31/022408 , H01L31/02327 , H01L31/105 , Y02E10/50
摘要： The invention relates to a radiation-sensitive device comprising a thin radiation-sensitive element (2), in particular a thin photodiode (2). The device includes a substrate (1) on which a photodiode (2) is provided. The surface (5) of the photodiode serves as a semi-pervious mirror (5) through which the radiation (100) enters; a reflecting layer (6) situated between the photodiode (2) and the substrate (1) also serves as a mirror (6). As a result, a so-called resonant cavity effect is possible, resulting, inter alia, in wavelength selectivity of the device. The known device has insufficient wavelength selectivity, which, in addition, cannot readily be set in an accurate and reproducible manner. A device in accordance with the invention is characterized in that the reflecting layer (6) is a metal layer (6) and in that the photodiode (2) is secured to the substrate (1) by means of an adhesive layer (7). By virtue of the high reflectivity of one (6) of the two mirrors (5, 6), the device has a great wavelength selectivity which, in addition, can be readily set in an accurate and reproducible manner. The adhesive layer (7) does not only enable the photodiode (7) to be secured to a substrate (1), which does not have to be a semiconductor substrate, but, this method of securing also enables a very attractive manufacturing method for the entire device to be achieved. A device in accordance with the invention can be advantageously used as a detector in a heterodyne or multiplex optical communication system or in an optical disc system.
摘要翻译：本发明涉及一种包括薄辐射敏感元件（2），特别是薄光电二极管（2）的辐射敏感器件。该器件包括其上设置有光电二极管（2）的衬底（1）。光电二极管的表面（5）用作半透明反射镜（5），辐射（100）通过该反射镜进入; 位于光电二极管（2）和基板（1）之间的反射层（6）也用作反射镜（6）。结果，所谓的谐振腔效应是可能的，特别是导致器件的波长选择性。已知的装置具有不充分的波长选择性，另外不能容易地以精确和可再现的方式设置。根据本发明的装置的特征在于反射层（6）是金属层（6）光电二极管（2）通过粘合剂层（7）固定到基底（1）上。由于两个反射镜（5,6）中的一个（6）的高反射率，该器件具有很大的波长选择性，此外，可以容易地以准确和可再现的方式设置。粘合剂层（7）不仅可以使光电二极管（7）固定到不必是半导体基板的基板（1）上，而且这种固定方法也可以使非常有吸引力的制造方法整个设备要实现。根据本发明的装置可以有利地用作外差或多路光通信系统或光盘系统中的检测器。

2. 发明授权

US5221856A Bipolar transistor with floating guard region under extrinsic base 失效
标题翻译：双极晶体管，外部基极具有浮动保护区域
公开(公告)号：US5221856A
公开(公告)日：1993-06-22
申请号：US833599
申请日：1992-02-10
申请人： Ronald Dekker , Martinus C. A. M. Koolen , Henricus G. R. Maas
发明人： Ronald Dekker , Martinus C. A. M. Koolen , Henricus G. R. Maas
IPC分类号： H01L21/225 , H01L21/285 , H01L21/32 , H01L21/3213 , H01L21/3215 , H01L21/331 , H01L21/60 , H01L29/732
CPC分类号： H01L21/76897 , H01L21/2257 , H01L21/28506 , H01L21/28525 , H01L21/32 , H01L21/32134 , H01L21/32155 , H01L29/66242 , H01L29/66272 , H01L29/7325
摘要： A first device region (10) of one conductivity type adjacent one major surface (1a) of a semiconductor body (1) has a relatively highly doped subsidiary region (11) spaced from the one major surface (1a) by a relatively lowly doped subsidiary region (12). A second device region (20) of the opposite conductivity type within the subsidiary region (12) has an intrinsic subsidiary region (21) and an extrinsic subsidiary region (23,24) surrounding the intrinsic subsidiary region (21) forming respective first and second pn junctions (22,25) with the relatively lowly doped subsidiary region (12). A third device region (30) of the one conductivity type is formed within the intrinsic subsidiary region (21) surface (1a). An additional region (60,60',61,62) is provided beneath the extrinsic subsidiary region (23,24) so as to lie within the spread of the depletion region (250) associated with the second pn junction (25) when the first and second pn junction (22,25) are reverse-biassed thereby extending the depletion region (250) beneath the emitter region (30) to cause an increase in the Early voltage (V.sub.eaf) of the device.
摘要翻译：与半导体本体（1）的一个主表面（1a）相邻的一种导电类型的第一器件区域（10）具有相对高度掺杂的辅助区域（11），该区域通过相对低掺杂的子元件与一个主表面（1a）间隔开区域（12）。在辅助区域（12）内具有相反导电类型的第二设备区域（20）具有内部辅助区域（21）和围绕内部辅助区域（21）的外在辅助区域（23,24），形成相应的第一和第二 pn结（22,25）与相对低掺杂的辅助区域（12）。一个导电类型的第三器件区域（30）形成在本征辅助区域（21）表面（1a）内。在外部辅助区域（23,24）的下方提供附加区域（60,60'，61,62），以便当位于与第二pn结（25）相关联的耗尽区域（250）的扩展区内时第一和第二pn结（22,25）被反向偏压，从而将耗尽区（250）延伸到发射极区（30）之下，以引起器件的早期电压（Veaf）的增加。

3. 发明授权

US4969026A Mesa bipolar transistor with edge contacts 失效
标题翻译：具有边缘触点的Mesa双极晶体管
公开(公告)号：US4969026A
公开(公告)日：1990-11-06
申请号：US506484
申请日：1990-04-06
申请人： Johannes W. A. Van der Velden , Henricus G. R. Maas , Marguerite M. C. Van Iersel-Schiffmacher
发明人： Johannes W. A. Van der Velden , Henricus G. R. Maas , Marguerite M. C. Van Iersel-Schiffmacher
IPC分类号： H01L29/73 , H01L21/331 , H01L29/423 , H01L29/732
CPC分类号： H01L29/42304 , H01L29/7325 , Y10S148/125
摘要： A semiconductor device having a monocrystalline silicon region (3) comprising a first zone (9) and an adjacent second zone (10) and laterally enclosed by a sunken oxide layer (4) and by an overlying highly doped polycrystalline silicon layer (5). The silicon layer (5) is laterally separated by an oxide layer (6) from the silicon region (3) and adjoins the first zone (9) on a narrow edge portion of the upper surface of the region (3), this zone being of the same conductivity type as the silicon layer (5). The second zone (10) is provided with an electrode layer (11). According to the invention, the silicon layer (5) is separated from the electrode layer (11) by an oxide strip (12A) formed in a self-aligned manner and at least one doped connection zone (13) having a width determined by the oxide strip (12A) is situated between the first and the second zones and located below the oxide strip (12A). The invention further relates to a method of manufacturing this device.

4. 发明授权

US4894702A High efficiency, small geometry semiconductor devices 失效
标题翻译：高效率，小几何半导体器件
公开(公告)号：US4894702A
公开(公告)日：1990-01-16
申请号：US163428
申请日：1988-03-03
申请人： Henricus G. R. Maas , Johannes W. A. Van Der Velden , Peter H. Kranen , Albertus T. M. Van De Goor , Date J. W. Noorlag
发明人： Henricus G. R. Maas , Johannes W. A. Van Der Velden , Peter H. Kranen , Albertus T. M. Van De Goor , Date J. W. Noorlag
IPC分类号： H01L29/73 , H01L21/285 , H01L21/331 , H01L21/336 , H01L21/763 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/732 , H01L29/735
CPC分类号： H01L29/735 , H01L21/28525 , H01L21/763 , H01L29/0653 , H01L29/41766 , H01L29/66272 , H01L29/66636 , H01L29/732 , H01L29/78
摘要： A semiconductor device comprising a first region, which is laterally bounded by a second region comprising a countersunk oxide layer and a highly doped polycrystalline silicon layer, which is disposed thereon and is covered by an oxide layer partly countersunk into it. The side edge of the polysilicon layer adjoins a contact zone, which is obtained by diffusion therefrom and is connected via a current path to a zone of a semiconductor circuit element. The upper side of the polysilicon layer is located at a higher level than that of the first region and the contact zone is connected to the said zone of the semiconductor circuit element via an intermediate region located in the first region below the second oxide layer and having a lower doping than the contact zone.

5. 发明授权

US4574468A Method of manufacturing a semiconductor device having narrow coplanar silicon electrodes 失效
标题翻译：制造具有窄共面硅电极的半导体器件的方法
公开(公告)号：US4574468A
公开(公告)日：1986-03-11
申请号：US657631
申请日：1984-10-04
申请人： Jan W. Slotboom , Henricus G. R. Maas , Johannes A. Appels , Francois M. Klaassen
发明人： Jan W. Slotboom , Henricus G. R. Maas , Johannes A. Appels , Francois M. Klaassen
IPC分类号： H01L29/762 , H01L21/033 , H01L21/339 , H01L27/10 , H01L29/76 , H01L29/772 , H01L21/90
CPC分类号： H01L29/66954 , H01L21/033
摘要： A method of manufacturing a semiconductor device, for example an SPS memory having narrow coplanar silicon electrodes. The electrodes are formed by etching grooves or slots (10) having a width in the submicron range into a polycrystalline silicon layer (3), the slot width being defined by the oxidized edge (6) of a silicon auxiliary layer (5). The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. According to the invention, the electrodes formed covered by silicon oxide (3B, 13B) are first interconnected pairwise, whereupon they are separated from each other in a separate etching step and are provided with self-aligned contact windows (15). Thus, the very narrow electrodes can be contacted without technological problems and memory cells of very small dimensions can be obtained.
摘要翻译：一种制造半导体器件的方法，例如具有窄共面硅电极的SPS存储器。通过将具有亚微米范围宽度的槽或槽（10）蚀刻成多晶硅层（3）形成电极，槽宽度由硅辅助层（5）的氧化边缘（6）限定。电极被氧化硅交替地覆盖，并且由包含氮化硅的层交替地覆盖。根据本发明，由氧化硅（3B，13B）覆盖的电极首先成对互连，于是它们在单独的蚀刻步骤中彼此分离并且设置有自对准的接触窗口（15）。因此，非常窄的电极可以在没有技术问题的情况下接触，并且可以获得非常小的尺寸的存储单元。

6. 发明授权

US06368921B1 Manufacture of trench-gate semiconductor devices 有权
标题翻译：沟槽栅半导体器件的制造
公开(公告)号：US06368921B1
公开(公告)日：2002-04-09
申请号：US09671888
申请日：2000-09-28
申请人： Erwin A. Hijzen , Henricus G. R. Maas , Cornelius E. Timmering
发明人： Erwin A. Hijzen , Henricus G. R. Maas , Cornelius E. Timmering
IPC分类号： H01L2336
CPC分类号： H01L29/66348
摘要： A trench-gate semiconductor device, for example a MOSFET or IGBT, of compact geometry is manufactured with self-aligned masking techniques in a simple process with good reproducibility. The source region (13) of the device is formed by introducing dopant (63) into an area of the body region (15) via a mask window (51a), diffusing the dopant to form a surface region (13b) that extends laterally below the mask (51) at a distance (d) beyond the masking edge (51b) of the window (51a), and then etching the body (10) at the window (51a) to form a trench (20) for the trench-gate (11) with a lateral extent (y) that is determined by the etching of the body (10) at the masking edge (51b) of the window (51a). A portion of the surface region (13b) is left to provide the source region (13) adjacent to the trench (20). The invention permits the etch edge definition for the trench (2) to be better controlled by using the masking edge (51b) of a well-defined mask (51), as compared with the less well defined edges that tend to result from the use of a side-wall extension in prior-art processes.
摘要翻译：具有紧凑几何形状的沟槽栅极半导体器件（例如MOSFET或IGBT）以简单的过程以自调整掩蔽技术制造，具有良好的再现性。通过掩模窗（51a）将掺杂剂（63）引入体区（15）的一个区域中形成器件的源极区（13），使掺杂剂扩散形成横向延伸的表面区域（13b）在窗口（51a）的掩蔽边缘（51b）之外的距离（d）处的掩模（51），然后在窗口（51a）处蚀刻主体（10），以形成用于沟槽门（11）具有通过在窗口（51a）的掩蔽边缘（51b）处对主体（10）的蚀刻确定的横向延伸（y）。留下表面区域（13b）的一部分以提供与沟槽（20）相邻的源极区域（13）。本发明允许通过使用明确定义的掩模（51）的掩模边缘（51b）来更好地控制沟槽（2）的蚀刻边缘定义，与通常由使用导致的较不明确的边缘相比较的现有技术中的侧壁延伸。

7. 发明授权

US5828122A Semiconductor body with a substrate glued to a support body 失效
标题翻译：具有胶合到支撑体上的基底的半导体体
公开(公告)号：US5828122A
公开(公告)日：1998-10-27
申请号：US815253
申请日：1997-03-12
申请人： Henricus G. R. Maas , Ronald Dekker , Theodorus M. Michielsen , Wilhelmus T. A. J. Van Den Einden
发明人： Henricus G. R. Maas , Ronald Dekker , Theodorus M. Michielsen , Wilhelmus T. A. J. Van Den Einden
IPC分类号： H01L27/12 , H01L21/02 , H01L21/58 , H01L23/04 , H01L23/10 , H01L23/16 , H01L23/64 , H01L29/00
CPC分类号： H01L24/83 , H01L23/04 , H01L23/10 , H01L24/26 , H01L2224/8319 , H01L2224/8385 , H01L2924/01013 , H01L2924/01058 , H01L2924/07802
摘要： A semiconductor device comprises a substrate (1) with a plane surface (4) on which a layer structure (2) is formed in a number of layers (5, 7, 9, 13, 15, 17). The side of the substrate on which the layer structure was formed is fastened to a plane support body (18) by means of a glue layer (19) which encompasses spacer elements (20). These spacer elements are fastened to the surface of the substrate and all have the same height measured from the surface (4). In fastening the substrate to the support body, glue is provided and the substrate is pressed onto the support body so that the pressure is evenly distributed over the spacer elements.
摘要翻译：半导体器件包括具有平面（4）的基板（1），层结构（2）在多个层（5,7,9,13,15,17）上形成。其上形成有层结构的基板的侧面通过包围间隔元件（20）的胶层（19）固定在平面支撑体（18）上。这些间隔元件固定在基片的表面上，并且都具有从表面（4）测量的相同的高度。在将基底固定到支撑体上时，提供胶水并将基底压在支撑体上，使得压力均匀地分布在间隔元件上。

8. 发明授权

US5753537A Method of manufacturing a semiconductor device for surface mounting 失效
标题翻译：制造用于表面安装的半导体器件的方法
公开(公告)号：US5753537A
公开(公告)日：1998-05-19
申请号：US792338
申请日：1997-01-31
申请人： Ronald Dekker , Henricus G. R. Maas , Martinus P. J. G. Versleijen
发明人： Ronald Dekker , Henricus G. R. Maas , Martinus P. J. G. Versleijen
IPC分类号： H01L21/60 , H01L21/68 , H01L21/762 , H01L23/48 , H01L23/482 , H01L21/44
CPC分类号： H01L21/76264 , H01L21/6835 , H01L23/481 , H01L23/4822 , H01L24/11 , H01L24/13 , H01L21/76289 , H01L2221/68359 , H01L2221/68363 , H01L2221/68377 , H01L2224/1308 , H01L2224/13099 , H01L2224/131 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/01061 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/12032 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/14 , H01L2924/30105
摘要： The invention relates to a method of manufacturing a semiconductor device (1) for surface mounting. Such a method is known, whereby such a semiconductor device is manufactured in that a semiconductor body with a semiconductor element is mounted on a metal lead frame with metal package leads, after which contact surfaces of the semiconductor element are connected to the package leads by means of bonding wires. It is found that semiconductor devices of small dimensions are difficult to realize by this known method, while in addition the manufacture of integrated circuits with very many package leads is comparatively expensive owing to the many connections which are to be made between the integrated circuits and the package leads. According to the invention, the semiconductor devices are packaged while they are still on a slice of semiconductor material, while the package leads are formed from the semiconductor material. In the method according to the invention, the semiconductor devices are manufactured without the necessity of a lead frame, bonding wires, or metal package leads. Thanks to the IC technologies at the wafer level, such as photolithography, etching, etc., the method according to the invention renders possible semiconductor devices of very small dimensions. In addition, integrated circuits with very many package leads can be manufactured in a simple manner without additional steps being necessary. The method according to the invention is thus comparatively inexpensive.
摘要翻译：本发明涉及制造用于表面安装的半导体器件（1）的方法。这种方法是已知的，由此制造这样的半导体器件，其中具有半导体元件的半导体本体安装在具有金属封装引线的金属引线框架上，之后半导体元件的接触表面通过装置连接到封装引线的接合线。发现通过这种已知的方法难以实现小尺寸的半导体器件，而另外由于在集成电路和集成电路之间需要进行许多连接，所以具有非常多的封装引线的集成电路的制造相当昂贵包装线根据本发明，半导体器件在它们仍然在半导体材料片上时被封装，而封装引线由半导体材料形成。在根据本发明的方法中，半导体器件被制造而不需要引线框架，接合线或金属封装引线。由于晶圆级的IC技术，例如光刻，蚀刻等，根据本发明的方法使得可能的尺寸非常小的半导体器件成为可能。此外，具有非常多的封装引线的集成电路可以以简单的方式制造而无需额外的步骤。因此，根据本发明的方法相对便宜。

9. 发明授权

US5405789A Method of manufacturing a semiconductor device whereby a laterally bounded semiconductor zone is formed in a semiconductor body in a self-aligning manner 失效
标题翻译：制造半导体器件的方法，由此横向界限的半导体区以自对准方式形成在半导体本体中
公开(公告)号：US5405789A
公开(公告)日：1995-04-11
申请号：US141888
申请日：1993-10-22
申请人： Ronald Dekker , Henricus G. R. Maas , Armand Pruijmboom , Wilhelmus T. A. J. Van Den Einden
发明人： Ronald Dekker , Henricus G. R. Maas , Armand Pruijmboom , Wilhelmus T. A. J. Van Den Einden
IPC分类号： H01L21/28 , H01L21/331 , H01L21/335 , H01L21/336 , H01L21/8249 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66303 , H01L21/28 , H01L21/8249 , H01L29/66416
摘要： A method of manufacturing a semiconductor device with a semiconductor element which includes a semiconductor zone (19) situated below an electrode (18) and adjoining a surface (5) of a semiconductor body (1), which semiconductor zone substantially does not project outside the electrode (18) in lateral direction. The electrode (18) is here formed on the surface (5) of the semiconductor body (1), after which semiconductor material adjoining the surface (5) and not covered by the electrode (18) is removed by an etching treatment, whereby the position of the semiconductor zone (19) below the electrode (18) is defined. Before the electrode (18) is formed, a surface zone (16) adjoining the surface (5) is formed in the semiconductor body (1) with a depth and a doping such as are desired for the semiconductor zone (19) to be formed below the electrode (18), after which the electrode (18) is formed on this surface zone and, during the etching treatment, the portion of the surface zone (16) not covered by the electrode (18) is etched away through its entire thickness. Conducting materials such as aluminium or aluminium alloys may be used for the electrode (18), i.e. materials which are not resistant to temperatures necessary for forming semiconductor zones through diffusion.
摘要翻译：一种制造具有半导体元件的半导体器件的方法，该半导体元件包括位于电极（18）下方并邻接半导体本体（1）的表面（5）的半导体区（19），该半导体区基本上不会突出在半导体本体电极（18）。此时，电极（18）形成在半导体本体（1）的表面（5）上，然后通过蚀刻处理去除邻接表面（5）并且未被电极（18）覆盖的半导体材料，由此，限定电极（18）下方的半导体区域（19）的位置。在形成电极（18）之前，在半导体本体（1）中形成与表面（5）相邻的表面区域（16），以形成半导体区域（19）所需的深度和掺杂在电极（18）的下方，之后在该表面区域上形成电极（18），并且在蚀刻处理期间，未被电极（18）覆盖的表面区域（16）的部分通过其整个厚度。可以使用诸如铝或铝合金的导电材料用于电极（18），即不耐受通过扩散形成半导体区域所需的温度的材料。

10. 发明授权

US5024956A Method of manufacturing a semiconductor device including mesa bipolar transistor with edge contacts 失效
标题翻译：制造包括具有边缘触点的台面双极晶体管的半导体器件的方法
公开(公告)号：US5024956A
公开(公告)日：1991-06-18
申请号：US534774
申请日：1990-06-07
申请人： Johannes W. A. Van Der Velden , Henricus G. R. Maas , Marguerite M. C. Van Iersel-Schiffmacher
发明人： Johannes W. A. Van Der Velden , Henricus G. R. Maas , Marguerite M. C. Van Iersel-Schiffmacher
IPC分类号： H01L29/73 , H01L21/331 , H01L29/423 , H01L29/732
CPC分类号： H01L29/42304 , H01L29/7325 , Y10S148/125
摘要： A method of manufacturing a semiconductor device having a monocrystalline silicon region (3) comprising a first zone (9) and an adjacent second zone (10) and laterally enclosed by a sunken oxide layer (4) and by an overlying highly doped polycrystalline silicon layer (5). The silicon layer (5) is laterally separated by an oxide layer (6) from the silicon region (3) and adjoins the first zone (9) on a narrow edge portion of the upper surface of the region (3), this zone being of the same conductivity type as the silicon layer (5). The second zone (10) is provided with an electrode layer (11). According to the invention, the silicon layer (5) is separated from the electrode layer (11) by an oxide strip (12A) formed in a self-aligned manner and at least one doped connection zone (13) having a width determined by said oxide strip (12A) is situated between said first and said second zones and located below said oxide strip (12A).

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