专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08643519B1 On-chip calibration method 有权
标题翻译：片上校准方法
公开(公告)号：US08643519B1
公开(公告)日：2014-02-04
申请号：US13367212
申请日：2012-02-06
申请人： Harold Kutz , Warren Synder , Bert Sullam , Dennis Seguine , Gajender Rohilla , Eashwar Thiagarajan
发明人： Harold Kutz , Warren Synder , Bert Sullam , Dennis Seguine , Gajender Rohilla , Eashwar Thiagarajan
IPC分类号： H03M1/10
CPC分类号： H03M1/1009 , H03M1/1061 , H03M1/12
摘要： A system for the calibration of a programmable system-on-a-chip is described. More specifically, embodiments of the present invention relate to a system that calibrates a programmable analog block in a system-on-a-chip without the use of external components.
摘要翻译：描述了用于校准可编程片上系统的系统。更具体地，本发明的实施例涉及在不使用外部组件的情况下校准片上系统中的可编程模拟块的系统。

2. 发明授权

US08125360B1 On-chip calibration method 有权
标题翻译：片上校准方法
公开(公告)号：US08125360B1
公开(公告)日：2012-02-28
申请号：US12776565
申请日：2010-05-10
申请人： Harold Kutz , Warren Synder , Bert Sullam , Dennis Seguine , Gajender Rohilla , Eashwar Thiagarajan
发明人： Harold Kutz , Warren Synder , Bert Sullam , Dennis Seguine , Gajender Rohilla , Eashwar Thiagarajan
IPC分类号： H03M1/10
CPC分类号： H03M1/1009 , H03M1/1061 , H03M1/12
摘要： A system for the calibration of a programmable system-on-a-chip is described. More specifically, embodiments of the present invention relate to a system that calibrates a programmable analog block in a system-on-a-chip without the use of external components.
摘要翻译：描述了用于校准可编程片上系统的系统。更具体地，本发明的实施例涉及在不使用外部组件的情况下校准片上系统中的可编程模拟块的系统。

3. 发明授权

US08487655B1 Combined analog architecture and functionality in a mixed-signal array 有权
公开(公告)号：US08487655B1
公开(公告)日：2013-07-16
申请号：US12774680
申请日：2010-05-05
申请人： Harold Kutz , Timothy Williams , Bert Sullam , Warren S. Snyder , James Shutt , Bruce Byrkett , Monte Mar , Eashwar Thiagarajan , Nathan Kohagen , David G. Wright , Mark Hastings , Dennis Seguine
发明人： Harold Kutz , Timothy Williams , Bert Sullam , Warren S. Snyder , James Shutt , Bruce Byrkett , Monte Mar , Eashwar Thiagarajan , Nathan Kohagen , David G. Wright , Mark Hastings , Dennis Seguine
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： G01R31/3177 , G01R31/31721 , G06F13/28 , H03K19/173
摘要： A system and apparatus are described for providing greater flexibility and performance in a mixed-signal array through improved and highly configurable routing, control elements and signal processing capabilities.

4. 发明授权

US09612987B2 Dynamically reconfigurable analog routing circuits and methods for system on a chip 有权
公开(公告)号：US09612987B2
公开(公告)日：2017-04-04
申请号：US12776323
申请日：2010-05-07
申请人： Bert Sullam , Harold Kutz , Timothy Williams , James Shutt , Bruce E. Byrkett , Melany Ann Richmond , Nathan Kohagen , Mark Hastings , Eashwar Thiagarajan , Warren Snyder
发明人： Bert Sullam , Harold Kutz , Timothy Williams , James Shutt , Bruce E. Byrkett , Melany Ann Richmond , Nathan Kohagen , Mark Hastings , Eashwar Thiagarajan , Warren Snyder
IPC分类号： H04L12/50 , G06F13/40
CPC分类号： G06F13/4022 , G06F2213/0038
摘要： An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.

5. 发明申请

US20110026519A1 DYNAMICALLY RECONFIGURABLE ANALOG ROUTING CIRCUITS AND METHODS FOR SYSTEM ON A CHIP 有权
标题翻译：动态系统的动态可重构模拟路由电路及方法
公开(公告)号：US20110026519A1
公开(公告)日：2011-02-03
申请号：US12776323
申请日：2010-05-07
申请人： Bert Sullam , Harold Kutz , Timothy Williams , James Shutt , Bruce E. Byrkett , Melany Ann Richmond , Nathan Kohagen , Mark Hastings , Eashwar Thiagarajan , Warren Snyder
发明人： Bert Sullam , Harold Kutz , Timothy Williams , James Shutt , Bruce E. Byrkett , Melany Ann Richmond , Nathan Kohagen , Mark Hastings , Eashwar Thiagarajan , Warren Snyder
IPC分类号： H04L12/50
CPC分类号： G06F13/4022 , G06F2213/0038
摘要： An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.
摘要翻译：集成电路装置可以包括可重新配置的模拟信号交换结构，其包括响应于可变模拟路由数据而被引脚连接电路选择性地连接到外部引脚的多个全局总线，以及选择性地连接到模拟块的多个局部总线和/或全局总线，通过响应于模拟路由数据路由连接电路; 以及响应于指令数据执行预定操作的至少一个处理器电路。

6. 发明授权

US07479913B1 Configurable analog to digital converter 有权
标题翻译：可配置的模数转换器
公开(公告)号：US07479913B1
公开(公告)日：2009-01-20
申请号：US11703873
申请日：2007-02-07
申请人： Eashwar Thiagarajan , Bert Sullam
发明人： Eashwar Thiagarajan , Bert Sullam
IPC分类号： H03M1/12
CPC分类号： H03M1/005 , H03M1/007 , H03M1/52 , H03M3/394 , H03M3/398 , H03M3/414
摘要： A configurable analog to digital converter (ADC) includes a plurality of analog units to integrate an input signal. The analog units are coupled together to generate a plurality of discrete-time signals responsive to the input signal and are further coupled to a plurality of bus segments via a plurality of interconnect circuits. Each interconnect circuit is configured to selectively couple the analog units to any of the bus segments.
摘要翻译：可配置的模数转换器（ADC）包括多个模拟单元以集成输入信号。模拟单元耦合在一起以响应于输入信号产生多个离散时间信号，并且还经由多个互连电路耦合到多个总线段。每个互连电路被配置为选择性地将模拟单元耦合到任何总线段。

7. 发明申请

US20080288755A1 CLOCK DRIVEN DYNAMIC DATAPATH CHAINING 有权
标题翻译：时钟驱动动态数据链
公开(公告)号：US20080288755A1
公开(公告)日：2008-11-20
申请号：US12104391
申请日：2008-04-16
申请人： Warren Synder , Bert Sullam
发明人： Warren Synder , Bert Sullam
IPC分类号： G06F9/302
CPC分类号： H03K19/17728
摘要： A system includes a plurality of datapaths, each having structural arithmetic elements to perform various arithmetic operations based, at least in part, on configuration data. The system also includes a configuration memory coupled to the datapaths, the configuration memory to provide the configuration data to the datapaths, which causes the datapaths to collaborate when performing the arithmetic operations.
摘要翻译：系统包括多个数据路径，每个数据路径具有至少部分地基于配置数据执行各种算术运算的结构运算元件。该系统还包括耦合到数据路径的配置存储器，配置存储器，用于向数据路径提供配置数据，这导致数据路径在执行算术运算时进行协作。

8. 发明授权

US06614320B1 System and method of providing a programmable clock architecture for an advanced microcontroller 有权
标题翻译：为高级微控制器提供可编程时钟架构的系统和方法
公开(公告)号：US06614320B1
公开(公告)日：2003-09-02
申请号：US10000383
申请日：2001-10-24
申请人： Bert Sullam , Harold Kutz
发明人： Bert Sullam , Harold Kutz
IPC分类号： H03B2800
CPC分类号： G06F1/32 , G06F1/06 , G06F1/08
摘要： One embodiment of the present invention is a programmable clock architecture for a microcontroller that provides multiple different clocking signal frequencies that may be utilized by one or more programmable logic blocks of the microcontroller. In this manner, the clocking architecture enables the programmable logic blocks to perform a wider variety of functions because they have access to a wider variety of clock signal frequencies. Specifically, the clocking architecture of the present embodiment includes a plurality of clocking sources. For example, the output clocking signal of one of the clock oscillators is divided down to different smaller frequencies and also multiplied to provide more frequencies that may be utilized by the programmable circuit blocks and processor of the microcontroller. Additionally, the clocking architecture includes a programmable option of utilizing precision clocking signals and/or less precise clocking signals depending on the desired applications of the microcontroller's programmable circuit blocks.
摘要翻译：本发明的一个实施例是用于微控制器的可编程时钟架构，其提供可由微控制器的一个或多个可编程逻辑块利用的多个不同的时钟信号频率。以这种方式，时钟架构使得可编程逻辑块能够执行更多种功能，因为它们可以访问更多种类的时钟信号频率。具体地，本实施例的时钟体系结构包括多个时钟源。例如，其中一个时钟振荡器的输出时钟信号被分成不同的较小频率，并且相乘以提供可被微控制器的可编程电路块和处理器利用的更多频率。此外，时钟架构包括根据微控制器的可编程电路块的期望应用利用精确时钟信号和/或更精确的时钟信号的可编程选项。

9. 发明授权

US09564902B2 Dynamically configurable and re-configurable data path 有权
标题翻译：动态配置和可重新配置的数据路径
公开(公告)号：US09564902B2
公开(公告)日：2017-02-07
申请号：US11968145
申请日：2007-12-31
申请人： Warren Synder , Bert Sullam
发明人： Warren Synder , Bert Sullam
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , H03K19/177
CPC分类号： H03K19/177
摘要： An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory.
摘要翻译：一种装置包括耦合到一个或多个结构运算元件的配置存储器，该配置存储器存储导致结构运算元件执行各种功能的值。该装置还包括系统控制器，用于使用值动态地加载配置存储器，并且提示结构运算元件根据配置存储器存储的值来执行功能。

10. 发明授权

US08516025B2 Clock driven dynamic datapath chaining 有权
标题翻译：时钟驱动动态数据路径链接
公开(公告)号：US08516025B2
公开(公告)日：2013-08-20
申请号：US12104391
申请日：2008-04-16
申请人： Warren Synder , Bert Sullam
发明人： Warren Synder , Bert Sullam
IPC分类号： G06F7/38
CPC分类号： H03K19/17728
摘要： A system includes a plurality of datapaths, each having structural arithmetic elements to perform various arithmetic operations based, at least in part, on configuration data. The system also includes a configuration memory coupled to the datapaths, the configuration memory to provide the configuration data to the datapaths, which causes the datapaths to collaborate when performing the arithmetic operations.
摘要翻译：系统包括多个数据路径，每个数据路径具有至少部分地基于配置数据执行各种算术运算的结构运算元件。该系统还包括耦合到数据路径的配置存储器，配置存储器，用于向数据路径提供配置数据，这导致数据路径在执行算术运算时进行协作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式