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    • 5. 发明授权
    • Programmable microcontroller architecture(mixed analog/digital)
    • 可编程微控制器架构(混合模拟/数字)
    • US07825688B1
    • 2010-11-02
    • US11799439
    • 2007-04-30
    • Warren SnyderMonte Mar
    • Warren SnyderMonte Mar
    • H01L25/00H03K19/177
    • H03K19/08G06F1/08G06F1/32G06F15/7867G06G7/06H03B5/364H03K3/012H03K3/014H03K3/02315H03K19/173H03K19/1733H03K19/177H03K19/17736H03K19/17748
    • A microcontroller with analog/digital Programmable System On-a-Chip (PSoC) architecture including multiple digital PSoC blocks and multiple analog PSoC blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The PSoC architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The PSoC array is programmed by flash memory and programming allows dynamic reconfiguration. That is, “on-the-fly” reconfiguration of the PSoC blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input/output data between all analog and digital blocks.
    • 具有模拟/数字可编程系统片上(PSoC)架构的微控制器,包括具有可编程互连结构的通信阵列中的多个数字PSoC模块和多个模拟PSoC模块。 单芯片设计通过集成可以相互通信的可编程数字和模拟电路块来实现。 闪存可编程的强大的模拟和数字模块可用于实现复杂的设计应用,否则将需要多个芯片和/或单独应用。 PSoC架构包括具有可编程数字模块的新型阵列,其可以使用可编程互连结构与可编程模拟块通信。 可编程模拟阵列包含连续时间(CT)块的补码和可以一起通信的开关电容(SC)块的补充。 模拟模块由可编程为一个或多个不同模拟功能的多功能电路组成,固定功能电路可编程,具有可变参数的固定功能。 数字模块包括标准多功能电路和具有不包括在标准数字电路中的功能的增强电路。 PSoC阵列由闪存编程,编程允许动态重新配置。 也就是说,允许PSoC块的“即时”重新配置。 具有连续时间模拟模块和开关电容模拟模块的可编程模拟阵列与可编程数字模块一起提供在单个芯片上。 可编程互连结构提供了所有模拟和数字模块之间的输入/输出数据的通信。
    • 10. 发明申请
    • Apparatus and Method for Programmable Power Management in a Programmable Analog Circuit Block
    • 可编程模拟电路块中可编程电源管理的装置和方法
    • US20120182073A1
    • 2012-07-19
    • US13328962
    • 2011-12-16
    • Monte Mar
    • Monte Mar
    • H03F3/04
    • G06F11/3652
    • An apparatus and method for programmable power management in a programmable analog circuit block. Specifically, the present invention describes an operational amplifier circuit that includes current sources that are coupled in parallel. Configuration bits are asserted to selectively enable or selectively disable one or more of the current sources in order to modulate the performance of the operational amplifier circuit block. Selective addition or removal of current sources increases or decreases the amount of current within the operational amplifier and, correspondingly, the speed and power consumption of the operational amplifier. Combinations of asserted configuration bits pass a bias voltage in order enable selected current sources. In one embodiment, the bias voltage can be increased in order to increase the current output of one of the current sources which, correspondingly, increases the speed of the operational amplifier circuit block.
    • 一种用于可编程模拟电路块中可编程电源管理的装置和方法。 具体地,本发明描述了一种运算放大器电路,其包括并联耦合的电流源。 配置位被置位以选择性地启用或选择性地禁用一个或多个电流源,以便调制运算放大器电路块的性能。 选择性地添加或去除电流源可以增加或减少运算放大器内的电流量,并相应地增加运算放大器的速度和功耗。 有效配置位的组合通过偏置电压,以便使能选定的电流源。 在一个实施例中,可以增加偏置电压,以便增加电流源中的一个的电流输出,相应地增加运算放大器电路块的速度。